Follow
Ping Lu
Ping Lu
Verified email at microsoft.com
Title
Cited by
Cited by
Year
A 3.6 mW, 90 nm CMOS gated-Vernier time-to-digital converter with an equivalent resolution of 3.2 ps
P Lu, A Liscidini, P Andreani
IEEE Journal of Solid-State Circuits 47 (7), 1626-1635, 2012
1402012
A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH -TDC for Low In-Band Phase Noise
Y Wu, M Shahmohammadi, Y Chen, P Lu, RB Staszewski
IEEE Journal of Solid-State Circuits 52 (7), 1885-1903, 2017
692017
A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise
Y Wu, M Shahmohammadi, Y Chen, P Lu, RB Staszewski
IEEE European Solid-State Circuits Conference 2016, 209-212, 2016
692016
A 2.2 ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration
P Lu, Y Wu, P Andreani
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (11), 1019 …, 2016
562016
A 2-D GRO vernier time-to-digital converter with large input range and small latency
P Lu, P Andreani, A Liscidini
Analog Integrated Circuit and Signal Processing 76, 195-206, 2013
382013
A 2-D GRO vernier time-to-digital converter with large input range and small latency
P Lu, P Andreani, A Liscidini
Radio Frequency Integrated Circuits Symposium (RFIC), 2013 IEEE, 151-154, 2013
382013
A 103fsrms1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL
Y Wu, P Lu, RB Staszewski
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 95-98, 2015
192015
A 90nm CMOS gated-ring-oscillator-based vernier time-to-digital converter for DPLLs
P Lu, P Andreani, A Liscidini
2011 Proceedings of the ESSCIRC (ESSCIRC), 459-462, 2011
152011
A 90nm CMOS digital PLL based on vernier-gated-ring-oscillator time-to-digital converter
P Lu, Y Wu, P Andreani
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2593-2596, 2012
142012
A 5.4 GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1 MHz resolution, and 180dB FOM
P Lu, H Sjoland
2008 NORCHIP, 223-226, 2008
122008
A 5GHz 90-nm CMOS all digital phase-locked loop
P Lu, H Sjöland
Analog integrated circuits and signal Processing 66, 49-59, 2011
112011
A 5GHz 90-nm CMOS all digital phase-locked loop
P Lu, H Sjöland
IEEE Asian Solid-State Circuit Conference (ASSCC), 65-68, 2009
112009
A high-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS
P Lu, P Andreani
NORCHIP 2010, 1-4, 2010
102010
A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction
Y Wu, P Lu, RB Staszewski
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (8), 2532-2545, 2020
82020
Metastable-free output synchronization for multiple-chip systems and the like
DF Pastorello, T Monk, P Lu, M Lu
US Patent 10,511,312, 2019
72019
Ultra-wideband transmitter design based on a new transmitted reference pulse cluster
Y Huo, X Dong, P Lu
ICT Express 3 (3), 142-147, 2017
72017
A 1-1 MASH 2-D vernier time-to-digital converter with 2nd-order noise shaping
P Lu, P Andreani
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1324-1327, 2014
72014
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter
P Lu, P Andreani, A Liscidini
NORCHIP 2012, 1-4, 2012
62012
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing
D Ye, P Lu, P Andreani, R Van Der Zee
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 169-172, 2013
42013
A 12-bit 125-MHz segmented current-steering DAC for communication application
C Tao, P Lu, N Li
2006 IET International Conference on Wireless, Mobile and Multimedia …, 2006
42006
The system can't perform the operation now. Try again later.
Articles 1–20