| On-chip deep neural network storage with multi-level eNVM M Donato, B Reagen, L Pentecost, U Gupta, D Brooks, GY Wei Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 18 | 2018 |
| MASR: A modular accelerator for sparse rnns U Gupta, B Reagen, L Pentecost, M Donato, T Tambe, AM Rush, GY Wei, ... 2019 28th International Conference on Parallel Architectures and Compilation …, 2019 | 15 | 2019 |
| Maxnvm: Maximizing dnn storage density and inference efficiency with sparse encoding and error mitigation L Pentecost, M Donato, B Reagen, U Gupta, S Ma, GY Wei, D Brooks Proceedings of the 52Nd Annual IEEE/ACM International Symposium on …, 2019 | 12 | 2019 |
| A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic M Donato, F Cremona, W Jin, RI Bahar, W Patterson, A Zaslavsky, ... Proceedings of the great lakes symposium on VLSI, 39-44, 2012 | 12 | 2012 |
| A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators P Whatmough, SK Lee, M Donato, HC Hsueh, SL Xi, U Gupta, ... 2019 IEEE Symposium on VLSI Circuits, 2019 | 9 | 2019 |
| Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS P Jannaty, FC Sabou, ST Le, M Donato, RI Bahar, W Patterson, J Mundy, ... Electron Devices, IEEE Transactions on 59 (3), 807-812, 2012 | 9 | 2012 |
| Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices with Reliable Long-Term Retention for Efficient Storage of Neural Network Weights S Ma, M Donato, SK Lee, D Brooks, GY Wei IEEE Electron Device Letters, 2019 | 6 | 2019 |
| A simulation framework for analyzing transient effects due to thermal noise in sub-threshold circuits M Donato, RI Bahar, W Patterson, A Zaslavsky Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 45-50, 2015 | 4 | 2015 |
| A fast simulator for the analysis of sub-threshold thermal noise transients M Donato, RI Bahar, W Patterson, A Zaslavsky Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 3 | 2016 |
| Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework P Jannaty, FC Sabou, ST Le, M Donato, RI Bahar, W Patterson, J Mundy, ... Electron Devices, IEEE Transactions on, 1-7, 0 | 3 | |
| MEMTI: Optimizing on-chip nonvolatile storage for visual multitask inference at the edge M Donato, L Pentecost, D Brooks, GY Wei IEEE Micro 39 (6), 73-81, 2019 | 2 | 2019 |
| A sub-threshold noise transient simulator based on integrated random telegraph and thermal noise modeling M Donato, RI Bahar, WR Patterson, A Zaslavsky IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 2 | 2017 |
| Design of error-resilient logic gates with reinforcement using implications X Han, M Donato, RI Bahar, A Zaslavsky, W Patterson 2016 International Great Lakes Symposium on VLSI (GLSVLSI), 191-196, 2016 | 2 | 2016 |
| A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm GG Ko, Y Chai, M Donato, PN Whatmough, T Tambe, RA Rutenbar, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 1 | 2020 |
| Fundamental thermal limits on data retention in low-voltage cmos latches and sram E Rezaei, M Donato, WR Patterson, A Zaslavsky, RI Bahar IEEE Transactions on Device and Materials Reliability 20 (3), 488-497, 2020 | 1 | 2020 |
| CHIPKIT: An agile, reusable open-source framework for rapid test chip development PN Whatmough, M Donato, GG Ko, SK Lee, D Brooks, GY Wei IEEE Micro 40 (4), 32-40, 2020 | 1 | 2020 |
| Thermal noise-induced error simulation framework for subthreshold CMOS SRAM E Rezaei, M Donato, WR Patterson, A Zaslavsky, RI Bahar Proc. SOI 3D Subthreshold Microelectron. Technol. Unified Conf.(S3S), 1-3, 2019 | 1 | 2019 |
| EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP T Tambe, C Hooper, L Pentecost, EY Yang, M Donato, V Sanh, AM Rush, ... arXiv preprint arXiv:2011.14203, 2020 | | 2020 |
| A Scalable Bayesian Inference Accelerator for Unsupervised Learning G Ko, Y Chai, M Donato, PN Whatmough, T Tambe, RA Rutenbar, GY Wei, ... 2020 IEEE Hot Chips 32 Symposium (HCS), 1-27, 2020 | | 2020 |
| SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devices Paul Whatmough, Sae Kyu Lee, Sam Xi, Udit Gupta, Lillian Pentecost, Marco ... Hot Chips 30: A Symposium on High Performance Chips, IEEE/ACM SIGARCH, 2018 | | 2018 |
Gu-Yeon WeiProfessor of EE and CS, Harvard UniversityEmail verificata su eecs.harvard.edu
