High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography P Agnello, T Ivers, C Warm, R Wise, R Wachnik, D Schepis, S Sankaran, ...
2006 International Electron Devices Meeting, 1-4, 2006
133 2006 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, ...
2012 International Electron Devices Meeting, 3.3. 1-3.3. 4, 2012
103 2012 Source and drain doping profile control employing carbon-doped semiconductor material V Ontalus, P Kulkarni, DR Wall, Z Zhu
US Patent 9,059,292, 2015
31 2015 Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions A Dube, V Ontalus
US Patent 8,394,712, 2013
30 2013 Structure and method for increasing strain in a device KK Chan, A Dube, VC Ontalus
US Patent 8,551,845, 2013
29 2013 Stressed channel FET with source/drain buffers JB Johnson, R Muralidhar, PJ Oldiges, VC Ontalus, K Xiu
US Patent 8,361,847, 2013
27 2013 Butted SOI junction isolation structures and devices and method of fabrication JB Johnson, S Narasimha, HM Nayfeh, V Ontalus, RR Robison
US Patent 8,741,725, 2014
25 2014 Method of fabricating a device using low temperature anneal processes, a device and design structure AG Domenicucci, TL Kane, S Narasimha, KA Nummy, V Ontalus, ...
US Patent 8,236,709, 2012
25 2012 Field effect transistor device KK Chan, A Dube, EC Harley, JR Holt, VC Ontalus, KT Schonenberg, ...
US Patent 8,492,234, 2013
23 2013 Semiconductor structures and methods of manufacturing the same X Li, VC Ontalus
US Patent 8,278,164, 2012
23 2012 Bi-layer nFET embedded stressor element and integration to enhance drive current KK Chan, A Dube, J Li, V Ontalus, Z Zhu
US Patent 8,035,141, 2011
23 2011 Pre-gate, source/drain strain layer formation JR Holt, VC Ontalus, KH Tabakman
US Patent App. 12/719,312, 2011
21 2011 Asymmetric source and drain stressor regions JB Johnson, VC Ontalus
US Patent App. 12/553,627, 2011
19 2011 Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels B Chandra, P Chang, GG Freeman, D Guo, JR Holt, A Kumar, TJ McArdle, ...
US Patent 8,940,595, 2015
18 2015 Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers D Chidambarrao, R Muralidhar, PJ Oldiges, V Ontalus
US Patent 8,541,814, 2013
14 2013 Activating dopants using multiple consecutive millisecond-range anneals O Gluschenkov, VC Ontalus, V Soler
US Patent 7,786,025, 2010
11 2010 SiGe HBTs with Integrated in 45nm PDSOI CMOS J Pekarik, V Jain, C Kenney, J Holt, S Khokale, S Saroop, JB Johnson, ...
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and …, 2021
9 2021 Replacement body FinFET for improved junction profile with gate self-aligned junctions V Ontalus
US Patent 9,761,720, 2017
9 2017 Monolayer dopant embedded stressor for advanced CMOS KK Chan, A Dube, JR Holt, J Li, JS Newbury, V Ontalus, DG Park, Z Zhu
US Patent 8,236,660, 2012
9 2012 Data mining to detect performance quality of tools used repetitively in manufacturing V Ontalus, JW Nam, Y Song
US Patent 7,337,033, 2008
8 2008