A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI M Blagojević, M Cochet, B Keller, P Flatresse, A Vladimirescu, B Nikolić
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016
76 2016 Resilient low voltage accelerators for high energy efficiency N Chandramoorthy, K Swaminathan, M Cochet, A Paidimarri, S Eldridge, ...
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
53 2019 8.4 a 0.33 v/-40 c process/temperature closed-loop compensation soc embedding all-digital clock multiplier and dc-dc converter exploiting fdsoi 28nm back-gate biasing S Clerc, M Saligane, F Abouzeid, M Cochet, JM Daveau, C Bottoni, D Bol, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
53 2015 A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI B Keller, M Cochet, B Zimmer, J Kwak, A Puggelli, Y Lee, M Blagojević, ...
IEEE Journal of Solid-State Circuits 52 (7), 1863-1875, 2017
52 2017 A 225 μm M Cochet, B Keller, S Clerc, F Abouzeid, A Cathelin, JL Autran, P Roche, ...
IEEE Solid-State Circuits Letters 1 (1), 14-17, 2018
35 2018 A 2.7 pJ/cycle 16 MHz, 0.7 G Lallement, F Abouzeid, M Cochet, JM Daveau, P Roche, JL Autran
IEEE Journal of Solid-State Circuits 53 (7), 2088-2100, 2018
32 2018 Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC B Keller, M Cochet, B Zimmer, Y Lee, M Blagojevic, J Kwak, A Puggelli, ...
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 269-272, 2016
21 2016 Light extraction efficiency Part A. Ray tracing for light extraction efficiency (LEE) modeling in nitride LEDs CL Keraly, L Kuritzky, M Cochet, C Weisbuch
III-Nitride Based Light Emitting Diodes and Applications 126, 231-269, 2013
20 2013 Ray tracing for light extraction efficiency (LEE) modeling in nitride LEDs C Lalau Keraly, L Kuritzky, M Cochet, C Weisbuch
III-Nitride Based Light Emitting Diodes and Applications, 301-340, 2017
18 2017 A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC T Jia, P Mantovani, MC Dos Santos, D Giri, J Zuckerman, EJ Loscalzo, ...
ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022
16 2022 A 2.7 pJ/cycle 16MHz SoC with 4.3 nW power-off ARM Cortex-M0+ core in 28nm FD-SOI G Lallement, F Abouzeid, M Cochet, JM Daveau, P Roche, JL Autran
ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 153-162, 2017
16 2017 A 72-GS/s, 8-bit DAC-based wireline transmitter in 4-nm FinFET CMOS for 200+ Gb/s serial links TO Dickson, ZT Deniz, M Cochet, TJ Beukema, M Kossel, T Morf, YH Choi, ...
IEEE Journal of Solid-State Circuits 58 (4), 1074-1086, 2022
13 2022 Very low voltage (VLV) design R Bertran, P Bose, D Brooks, J Burns, A Buyuktosunoglu, ...
2017 IEEE International Conference on Computer Design (ICCD), 601-604, 2017
11 2017 A 28nm FD-SOI standard cell 0.6–1.2 V open-loop frequency multiplier for low power SoC clocking M Cochet, S Clerc, M Naceur, P Schamberger, D Croain, JL Autran, ...
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1206-1209, 2016
7 2016 Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI M Cochet, B Pelloux-Prayer, M Saligane, S Clerc, P Roche, JL Autran, ...
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2014
7 2014 An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS AS Yonar, PA Francese, M Brändli, M Kossel, T Morf, JE Proesel, S Rylov, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
6 2022 A scalable methodology for agile chip development with open-source hardware components MC Santos, T Jia, M Cochet, K Swaminathan, J Zuckerman, P Mantovani, ...
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022
4 2022 On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC M Cochet, A Puggelli, B Keller, B Zimmer, M Blagojevic, S Clerc, P Roche, ...
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 125-128, 2016
4 2016 A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking M Cochet, S Clerc, G Lallement, F Abouzeid, P Roche, JL Autran
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 69-72, 2017
2 2017 Device for generating a clock signal by frequency multiplication M Cochet, S Clerc
US Patent 9,634,671, 2017
2 2017 
Philippe RocheFellowEmail verificata su st.com
