| An event-driven clockless level-crossing ADC with signal-dependent adaptive resolution C Weltin-Wu, Y Tsividis IEEE Journal of Solid-State Circuits 48 (9), 2180-2190, 2013 | 141 | 2013 |
| A 3 GHz fractional all-digital PLL with a 1.8 MHz bandwidth implementing spur reduction techniques E Temporiti, C Weltin-Wu, D Baldi, R Tonietto, F Svelto IEEE Journal of Solid-State Circuits 44 (3), 824-834, 2009 | 137 | 2009 |
| A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation E Temporiti, C Weltin-Wu, D Baldi, M Cusmai, F Svelto IEEE Journal of Solid-State Circuits 45 (12), 2723-2736, 2010 | 116 | 2010 |
| A 3GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction C Weltin-Wu, E Temporiti, D Baldi, F Svelto 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 60 | 2008 |
| Event-driven GHz-range continuous-time digital signal processor with activity-dependent power dissipation M Kurchuk, C Weltin-Wu, D Morche, Y Tsividis IEEE Journal of Solid-State Circuits 47 (9), 2164-2173, 2012 | 47 | 2012 |
| Understanding phase error and jitter: Definitions, implications, simulations, and measurement I Galton, C Weltin-Wu IEEE Transactions on Circuits and Systems I: Regular Papers 66 (1), 1-19, 2018 | 42 | 2018 |
| An event-driven, alias-free ADC with signal-dependent resolution C Weltin-Wu, Y Tsividis 2012 Symposium on VLSI Circuits (VLSIC), 28-29, 2012 | 39 | 2012 |
| A 3.5 GHz digital fractional-PLL frequency synthesizer based on ring oscillator frequency-to-digital conversion C Weltin-Wu, G Zhao, I Galton IEEE Journal of Solid-State Circuits 50 (12), 2988-3002, 2015 | 30 | 2015 |
| Time-interleaved digital-to-time converter C Weltin-wu, Y Huang, M Seth US Patent 8,860,514, 2014 | 28 | 2014 |
| A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation C Weltin-Wu, E Temporiti, D Baldi, M Cusmai, F Svelto 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 468-469, 2010 | 28 | 2010 |
| GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity M Kurchuk, C Weltin-Wu, D Morche, Y Tsividis 2011 IEEE International Solid-State Circuits Conference, 232-234, 2011 | 20 | 2011 |
| Frequency synthesizer with hit-less transitions between frequency-and phase-locked modes C Weltin-wu, Y Huang US Patent 8,786,341, 2014 | 19 | 2014 |
| Method of improving noise characteristics of an ADPLL and a relative ADPLL C Weltin-wu, EST Milani, D Baldi US Patent 7,940,099, 2011 | 18 | 2011 |
| Digital fractional-N PLL based upon ring oscillator delta-sigma frequency conversion I Galton, C Weltin-wu US Patent 10,158,366, 2018 | 14 | 2018 |
| Systems, devices, and methods for continuous-time digital signal processing and signal representation M Kurchuk, C Weltin-wu, Y Tsividis, D Morche, D Lachartre US Patent 8,749,421, 2014 | 14 | 2014 |
| Insights into wideband fractional ADPLLs: Modeling and calibration of nonlinearity induced fractional spurs C Weltin-Wu, E Temporiti, M Cusmai, D Baldi, F Svelto IEEE Transactions on Circuits and Systems I: Regular Papers 57 (9), 2259-2268, 2010 | 14 | 2010 |
| Insights into wideband fractional all-digital PLLs for RF applications E Temporiti, C Weltin-Wu, D Baldi, R Tonietto, F Svelto 2009 IEEE Custom Integrated Circuits Conference, 37-44, 2009 | 13 | 2009 |
| 25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation C Weltin-Wu, G Zhao, I Galton 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 12 | 2015 |
| A Linearized Model for the Design of Fractional- Digital PLLs Based on Dual-Mode Ring Oscillator FDCs C Weltin-Wu, E Familier, I Galton IEEE Transactions on Circuits and Systems I: Regular Papers 62 (8), 2013-2023, 2015 | 10 | 2015 |
| Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs E Alvarez-Fontecilla, AI Eissa, E Helal, C Weltin-Wu, I Galton IEEE Transactions on Circuits and Systems I: Regular Papers 68 (3), 965-974, 2020 | 6 | 2020 |
Ian GaltonUniversity of California, San DiegoVerified email at eng.ucsd.edu
