| Ultra-low power flexible precision FeFET based analog in-memory computing T Soliman, F Müller, T Kirchner, T Hoffmann, H Ganem, E Karimov, T Ali, ... 2020 IEEE International Electron Devices Meeting (IEDM), 29.2. 1-29.2. 4, 2020 | 82 | 2020 |
| Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving M Jung, SA McKee, C Sudarshan, C Dropmann, C Weis, N Wehn Proceedings of the International Symposium on Memory Systems, 377-386, 2018 | 22 | 2018 |
| An analysis on retention error behavior and power consumption of recent DDR4 DRAMs DM Mathew, M Schultheis, CC Rheinländer, C Sudarshan, C Weis, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 293-296, 2018 | 22 | 2018 |
| A lean, low power, low latency DRAM memory controller for transprecision computing C Sudarshan, J Lappas, C Weis, DM Mathew, M Jung, N Wehn Embedded Computer Systems: Architectures, Modeling, and Simulation: 19th …, 2019 | 20 | 2019 |
| Improving the error behavior of DRAM by exploiting its Z-channel property K Kraft, C Sudarshan, DM Mathew, C Weis, N Wehn, M Jung 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 19 | 2018 |
| An in-dram neural network processing engine C Sudarshan, J Lappas, MM Ghaffar, V Rybalkin, C Weis, M Jung, ... 2019 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2019 | 17 | 2019 |
| eBrainII: a 3 kW realtime custom 3D DRAM integrated ASIC implementation of a biologically plausible model of a human scale cortex D Stathis, C Sudarshan, Y Yang, M Jung, C Weis, A Hemani, A Lansner, ... Journal of Signal Processing Systems 92, 1323-1343, 2020 | 15 | 2020 |
| Efficient hardware architectures for 1D-and MD-LSTM networks V Rybalkin, C Sudarshan, C Weis, J Lappas, N Wehn, L Cheng Journal of Signal Processing Systems 92, 1219-1245, 2020 | 12 | 2020 |
| A low power in-DRAM architecture for quantized CNNs using fast Winograd convolutions MM Ghaffar, C Sudarshan, C Weis, M Jung, N Wehn Proceedings of the International Symposium on Memory Systems, 158-168, 2020 | 12 | 2020 |
| A novel DRAM-based process-in-memory architecture and its implementation for CNNs C Sudarshan, T Soliman, C De la Parra, C Weis, L Ecco, M Jung, N Wehn, ... Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 9 | 2021 |
| Fast validation of DRAM protocols with timed petri nets M Jung, K Kraft, T Soliman, C Sudarshan, C Weis, N Wehn Proceedings of the International Symposium on Memory Systems, 133-147, 2019 | 7 | 2019 |
| ZuSE Ki-Avf: application-specific AI processor for intelligent sensor signal processing in autonomous driving GB Thieu, S Gesper, G Payá-Vayá, C Riggers, O Renke, T Fiedler, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 5 | 2023 |
| Optimization of DRAM based PIM architecture for energy-efficient deep neural network training C Sudarshan, MH Sadi, C Weis, N Wehn 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1472-1476, 2022 | 5 | 2022 |
| Efficient coding scheme for DDR4 memory subsystems K Kraft, DM Mathew, C Sudarshan, M Jung, C Weis, N Wehn, F Longnos Proceedings of the International Symposium on Memory Systems, 148-157, 2018 | 5 | 2018 |
| The role of memories in transprecision computing C Weis, M Jung, ÉF Zulian, C Sudarshan, DM Mathew, N Wehn 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 5 | 2018 |
| A critical assessment of dram-pim architectures-trends, challenges and solutions C Sudarshan, MH Sadi, L Steiner, C Weis, N Wehn International Conference on Embedded Computer Systems, 362-379, 2022 | 4 | 2022 |
| Efficient generation of application specific memory controllers MV Natale, M Jung, K Kraft, F Lauer, J Feldmann, C Sudarshan, C Weis, ... Proceedings of the International Symposium on Memory Systems, 233-247, 2020 | 4 | 2020 |
| Channel models for physical unclonable functions based on DRAM retention measurements S Müelich, S Bitzer, C Sudarshan, C Weis, N Wehn, M Bossert, ... 2019 XVI International Symposium" Problems of Redundancy in Information and …, 2019 | 4 | 2019 |
| A weighted current summation based mixed signal DRAM-PIM architecture for deep neural network inference C Sudarshan, T Soliman, J Lappas, C Weis, MH Sadi, M Jung, A Guntoro, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022 | 3 | 2022 |
| A novel DRAM architecture for improved bandwidth utilization and latency reduction using dual-page operation C Sudarshan, L Steiner, M Jung, J Lappas, C Weis, N Wehn IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1615-1619, 2021 | 3 | 2021 |
Norbert WehnUniversity of KaiserslauternVerified email at eit.uni-kl.de
