A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ... IEEE Journal of Solid-State Circuits 50 (1), 68-80, 2014 | 94 | 2014 |

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration A Musa, W Deng, T Siriburanon, M Miyahara, K Okada, A Matsuzawa IEEE Journal of Solid-State Circuits 49 (1), 50-60, 2014 | 93 | 2014 |

Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing W Deng, K Okada, A Matsuzawa IEEE Journal of Solid-State Circuits 2 (48), 429-440, 2013 | 74 | 2013 |

A Fractional-*N* Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dBAT Narayanan, M Katsuragi, K Kimura, S Kondo, KK Tokgoz, K Nakata, ... IEEE Journal of Solid-State Circuits 51 (7), 1630-1640, 2016 | 60 | 2016 |

A 0.0066 mm 2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ... Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, 2014 | 60* | 2014 |

A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11 ad T Siriburanon, S Kondo, M Katsuragi, H Liu, K Kimura, W Deng, K Okada, ... IEEE Journal of Solid-State Circuits 51 (5), 1246-1260, 2016 | 55 | 2016 |

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers W Deng, T Siriburanon, A Musa, K Okada, A Matsuzawa IEEE Journal of Solid-State Circuits 7 (48), 1710-1720, 2013 | 55 | 2013 |

A 0.022mm^{2}970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuitsW Deng, A Musa, T Siriburanon, M Miyahara, K Okada, A Matsuzawa 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 49 | 2013 |

A 2.2 GHz-242 dB-FOM 4.2 mW ADC-PLL using digital sub-sampling architecture T Siriburanon, S Kondo, K Kimura, T Ueno, S Kawashima, T Kaneko, ... IEEE Journal of Solid-State Circuits 51 (6), 1385-1397, 2016 | 45 | 2016 |

14.1 A 0.048mm^{2} 3mW synthesizable fractional-N PLL with a soft injection-locking techniqueW Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 45 | 2015 |

A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators T Siriburanon, T Ueno, K Kimura, S Kondo, W Deng, K Okada, ... 2014 IEEE radio frequency integrated circuits symposium, 105-108, 2014 | 30 | 2014 |

An ADPLL-centric bluetooth low-energy transceiver with 2.3 mW interference-tolerant hybrid-loop receiver and 2.9 mW single-point polar transmitter in 65nm CMOS H Liu, Z Sun, D Tang, H Huang, T Kaneko, W Deng, R Wu, K Okada, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 444-446, 2018 | 26 | 2018 |

A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing W Deng, K Okada, A Matsuzawa 2011 Proceedings of the ESSCIRC (ESSCIRC), 499-502, 2011 | 23 | 2011 |

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular T Siriburanon, H Liu, K Nakata, W Deng, JH Son, DY Lee, K Okada, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 22 | 2015 |

A 13.2% locking-range divide-by-6, 3.1 mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs T Siriburanon, W Deng, A Musa, K Okada, A Matsuzawa 2013 Proceedings of the ESSCIRC (ESSCIRC), 403-406, 2013 | 21 | 2013 |

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios W Deng, S Hara, A Musa, K Okada, A Matsuzawa IEEE Journal of Solid-State Circuits 49 (9), 1984-1994, 2014 | 19 | 2014 |

A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS H Liu, D Tang, Z Sun, W Deng, HC Ngo, K Okada, A Matsuzawa 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 246-248, 2018 | 17 | 2018 |

A DPLL-centric Bluetooth low-energy transceiver with a 2.3-mW interference-tolerant hybrid-loop receiver in 65-nm CMOS H Liu, Z Sun, D Tang, H Huang, T Kaneko, Z Chen, W Deng, R Wu, ... IEEE Journal of Solid-State Circuits 53 (12), 3672-3687, 2018 | 15 | 2018 |

A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation W Deng, K Okada, A Matsuzawa 2010 IEEE Asian Solid-State Circuits Conference, 1-4, 2010 | 15 | 2010 |

A 60-GHz efficiency-enhanced on-chip dipole antenna using helium-3 ion implantation process R Wu, W Deng, S Sato, T Hirano, N Li, T Inoue, H Sakane, K Okada, ... 2014 44th European Microwave Conference, 108-111, 2014 | 14 | 2014 |