Payman Behnam
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A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs
B Alizadeh, P Behnam, S Sadeghi-kohan
IEEE Transactions on Computers 64 (6), 1564-1578, 2015
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs
B Alizadeh, P Behnam
Microprocessors and Microsystems 37 (8), 1108-1121, 2013
In-circuit mutation-based automatic correction of certain design errors using SAT mechanisms
P Behnam, B Alizadeh
2015 IEEE 24th Asian Test Symposium (ATS), 199-204, 2015
Accelerating-Medians Clustering Using a Novel 4T-4R RRAM Cell
YK Rupesh, P Behnam, GR Pandla, M Miryala, MN Bojnordi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
High-Speed Hardware Implementation of Fixed and Run-time Variable Window Length 1-D Median Filters
E Nikahd, P Behnam, R Sameni
IEEE Transactions on Circuits and Systems II 63 (5), 478 - 482, 2016
Formal verification and debugging of array dividers with auto-correction mechanism
MH Haghbayan, B Alizadeh, P Behnam, S Safari
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
Automatic correction of certain design errors using mutation technique.
P Behnam, B Alizadeh, Z Navabi
2014 19th IEEE European Test Symposium (ETS), 1-2, 2014
Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines
S Taheri, J Heo, P Behnam, J Chen, A Veidenbaum, A Nicolau
26'th IEEE International Symposium on Field-Programmable Custom Computing …, 2018
Reducing search space for fault diagnosis: A probability-based scoring approach
H Sabaghian-Bidgoli, P Behnam, B Alizadeh, Z Navabi
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 545-550, 2017
Improving polynomial datapath debugging with HEDs
S Sadeghi-Kohan, P Behnam, B Alizadeh, M Fujita, Z Navabi
2014 19th IEEE European Test Symposium (ETS), 1-6, 2014
A probabilistic approach for counterexample generation to aid design debugging
P Behnam, H Sabaghian-Bidgoli, B Alizadeh, K Mohajerani, Z Navabi
East-West Design & Test Symposium (EWDTS 2013), 1-5, 2013
Mutation Based Debugging Technique with Auto-Correction Mechanism for RTL Designs
P Behnam, B Alizadeh, Z Navabi, M Fujita
8'th IEEE International Workshop of Silicon Debug and Diagnosis (SDD), in …, 2012
Affix: Automatic acceleration framework for fpga implementation of openvx vision algorithms
S Taheri, P Behnam, E Bozorgzadeh, A Veidenbaum, A Nicolau
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
Formally analyzing fault tolerance in datapath designs using equivalence checking
P Behnam, B Alizadeh, S Taheri, M Fujita
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 133-138, 2016
Hybrid history-based test overlapping to reduce test application time
V Janfaza, B Forouzandeh, P Behnam, M Najafi
Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014), 1-4, 2014
R-cache: A highly set-associative in-package cache using memristive arrays
P Behnam, AP Chowdhury, MN Bojnordi
2018 IEEE 36th International Conference on Computer Design (ICCD), 423-430, 2018
Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures
P Behnam, N Sedaghati, M Nazm Bojnordi
ACM Workshop on Energy Efficient Supercomputing (E2SC) held in conjunction …, 2017
A low-power enhanced bitmask-dictionary scheme for test data compression
V Janfaza, P Behnam, B Forouzandeh, B Alizadeh
2014 IEEE Computer Society Annual Symposium on VLSI, 220-225, 2014
STFL: Energy-efficient data movement with slow transition fast level signaling
P Behnam, MN Bojnordi
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs
P Behnam, B Alizadeh, S Taheri
arXiv preprint arXiv:1712.09818, 2017
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