Luis Guerra e Silva
Luis Guerra e Silva
INESC-ID, Instituto Superior Técnico, ULisbon
Verified email at inesc-id.pt
TitleCited byYear
Algorithms for solving boolean satisfiability in combinational circuits
LG e Silva, LM Silveira, J Marques-Silva
Design, Automation and Test in Europe Conference and Exhibition, 1999 …, 1999
661999
Satisfiability models and algorithms for circuit delay computation
LG e Silva, J Marques-Silva, LM Silveira, KA Sakallah
ACM Transactions on Design Automation of Electronic Systems 7 (1), 137-158, 2002
392002
Timing analysis using propositional satisfiability
LG Silva, JM Silva, LM Silveira, KA Skallah
1998 IEEE International Conference on Electronics, Circuits and Systems …, 1998
341998
Solving satisfiability in combinational circuits with backtrack search and recursive learning
JP Marques-Silva, LG e Silva
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat …, 1999
271999
Realistic delay modeling in satisfiability-based timing analysis
LG e Silva, JPM Silva, LM Silveira, KA Sakallah
ISCAS'98. Proceedings of the 1998 IEEE International Symposium on Circuits …, 1998
271998
Solving satisfiability in combinational circuits
J Marques-Silva, LG e Silva
IEEE Design & Test of Computers 20 (4), 16-21, 2003
252003
Efficient computation of the worst-delay corner
LG e Silva, LM Silveira, JR Phillips
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
212007
TAU 2013 variation aware timing analysis contest
D Sinha, L Guerra e Silva, J Wang, S Raghunathan, D Netrabile, ...
Proceedings of the 2013 ACM International symposium on Physical Design, 171-178, 2013
102013
Variation-aware, library compatible delay modeling strategy
LGE Silva, Z Zhu, JR Phillips, LM Silveira
2006 IFIP International Conference on Very Large Scale Integration, 122-127, 2006
92006
Branch and bound techniques for computation of critical timing conditions
LG e Silva, LM Silveira, J Phillips
US Patent 8,245,167, 2012
72012
Effective corner-based techniques for variation-aware IC timing verification
LG e Silva, J Phillips, LM Silveira
IEEE transactions on computer-aided design of integrated circuits and …, 2009
62009
Branch and bound techniques for computation of critical timing conditions
LG e Silva, LM Silveira, J Phillips
US Patent 8,799,840, 2014
42014
Satisfiability models and algorithms for circuit delay computation
L Guerra e Silva, J Marques-Silva, LM Silveira, KA Sakallah
ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 (1 …, 2002
42002
Library compatible variational delay computation
LG e Silva, Z Zhu, JR Phillips, LM Silveira
VLSI-SoC: Research Trends in VLSI and Systems on Chip, 157-176, 2008
22008
Improving SAT solver efficiency using a multi-core approach
R Marques, LG Silva, P Flores, LM Silveira
The Twenty-Sixth International FLAIRS Conference, 2013
12013
Handling intra-die variations in PSTA
L Guerra e Silva, LM Silveira
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
12011
Speedpath analysis under parametric timing models
L Guerra e Silva, JR Phillips, LM Silveira
Proceedings of the 47th Design Automation Conference, 268-273, 2010
12010
Efficient computation of the exact worst-delay corner
LG e Silva, J Phillips, LM Silveira
IEEE/ACM International Workshop on Timing Issues in the Specification and …, 2007
12007
Static Circuit Tuning
C Visweswariah, AR Conn, LG Silva
High Performance Algorithms and Software for Nonlinear Optimization 82, 363, 2013
2013
cmcSAT-A Cooperative MultiCore SAT Solver
R Marques, LG Silva, P Flores, LM Silveira
2012
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