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Marco Pagani
Marco Pagani
Red Hat
Verified email at redhat.com
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Year
A framework for supporting real-time applications on dynamic reconfigurable FPGAs
A Biondi, A Balsini, M Pagani, E Rossi, M Marinoni, G Buttazzo
2016 IEEE Real-Time Systems Symposium (RTSS), 1-12, 2016
702016
Is your bus arbiter really fair? restoring fairness in axi interconnects for fpga socs
F Restuccia, M Pagani, A Biondi, M Marinoni, G Buttazzo
ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-22, 2019
232019
ARTE: arduino real-time extension for programming multitasking applications
P Buonocunto, A Biondi, M Pagani, M Marinoni, G Buttazzo
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 1724-1731, 2016
222016
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs
F Restuccia, M Pagani, A Biondi, M Marinoni, G Buttazzo
32nd Euromicro Conference on Real-Time Systems (ECRTS 2020), 2020
182020
A bandwidth reservation mechanism for AXI-based hardware accelerators on FPGAs
M Pagani, E Rossi, A Biondi, M Marinoni, G Lipari, G Buttazzo
31st Euromicro Conference on Real-Time Systems (ECRTS 2019), 2019
172019
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration
M Pagani, A Balsini, A Biondi, M Marinoni, G Buttazzo
2017 30th IEEE International System-on-Chip Conference (SOCC), 96-101, 2017
142017
Towards real-time operating systems for heterogeneous reconfigurable platforms
M Pagani, M Marinoni, A Biondi, A Balsini, G Buttazzo
12th Workshop on Operating Systems Platforms for Embedded Real-Time …, 2016
112016
Spatio-temporal optimization of deep neural networks for reconfigurable fpga socs
B Seyoum, M Pagani, A Biondi, S Balleri, G Buttazzo
IEEE Transactions on Computers 70 (11), 1988-2000, 2020
92020
Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC
B Seyoum, M Pagani, A Biondi, G Buttazzo
Proceedings of the 36th Annual ACM Symposium on Applied Computing, 481-490, 2021
22021
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact).
F Restuccia, M Pagani, A Biondi, M Marinoni, GC Buttazzo
Dagstuhl Artifacts Ser. 6 (1), 04:1-04:3, 2020
12020
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs
F Restuccia, M Pagani, A Biondi, M Marinoni, G Buttazzo
IEEE Transactions on Computers, 2022
2022
ARTe: Providing real-time multitasking to Arduino
F Restuccia, M Pagani, A Mascitti, M Barrow, M Marinoni, A Biondi, ...
Journal of Systems and Software 186, 111185, 2022
2022
The Journal of Systems & Software
F Restuccia, M Pagani, A Mascitti, M Barrow, M Marinoni, A Biondi, ...
2021
Techniques pour l’amélioration de la prévisibilité de l’accélération matérielle pour les plateformes informatiques hétérogènes SoC-FPGA
M Pagani
2020
Enabling Predictable Hardware Acceleration in Heterogeneous SoC-FPGA Computing Platforms
M Pagani
Université de Lille; Scuola superiore Sant'Anna di studi universitari e di …, 2020
2020
Software support for dynamic partial reconfigurable FPGAs on heterogeneous platforms
M Pagani
2016
List of Secondary Reviewers
L Abeni, SA Rashid, N Ackerman, B Alahmad, MA Awan, J An, ...
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