Ramesh Harjani
Ramesh Harjani
E. F. Johnson Professor, Electrical & Computer Engineering, University of Minnesota
Verified email at ece.umn.edu - Homepage
Title
Cited by
Cited by
Year
OASYS: A framework for analog circuit synthesis
R Harjani, RA Rutenbar, LR Carley
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989
5111989
A high-efficiency DC–DC converter using 2 nH integrated inductors
J Wibben, R Harjani
IEEE Journal of Solid-State Circuits 43 (4), 844-854, 2008
3332008
A low-power CMOS VGA for 50 Mb/s disk drive read channels
R Harjani
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1995
2591995
Design of low-phase-noise CMOS ring oscillators
L Dai, R Harjani
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002
1462002
A prototype framework for knowledge-based analog circuit synthesis
R Harjani, RA Rutenbar, LR Carley
Proceedings of the 24th ACM/IEEE Design Automation Conference, 42-49, 1987
1281987
Fully-integrated on-chip DC-DC converter with a 450X output range
SS Kudva, R Harjani
IEEE Journal of Solid-State Circuits 46 (8), 1940-1951, 2011
1222011
CMOS switched-op-amp-based sample-and-hold circuit
L Dai, R Harjani
IEEE journal of solid-state circuits 35 (1), 109-113, 2000
1222000
A+ 18 dBm IIP3 LNA in 0.35/spl mu/m CMOS
Y Ding, R Harjani
2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001
1132001
Partial positive feedback for gain enhancement of low-power CMOS OTAs
R Wang, R Harjani
Low-Voltage Low-Power Analog Integrated Circuits, 21-35, 1995
1051995
Design of high-performance CMOS voltage-controlled oscillators
L Dai, R Harjani
Springer Science & Business Media, 2012
942012
/spl Sigma/High-frequency LC VCO design using capacitive degeneration
B Jung, R Harjani
IEEE Journal of Solid-State Circuits 39 (12), 2359-2370, 2004
852004
High-frequency LC VCO design using capacitive degeneration
B Jung, R Harjani
Solid-State Circuits, IEEE Journal of 39 (12), 2359-2370, 2004
84*2004
A linearized, low phase noise VCO based 25 GHz PLL with automatic biasing
B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, J Plouchart, AV Rylyakov, ...
IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013
792013
A high-efficiency CMOS +22-dBm linear power amplifier
Y Ding, R Harjani
Solid-State Circuits, IEEE Journal of 40 (9), 1895-1900, 2005
742005
An integrated low-voltage class AB CMOS OTA
R Harjani, R Heineke, F Wang
IEEE Journal of Solid-State Circuits 34 (2), 134-142, 1999
731999
Analog/RF physical layer issues for UWB systems
R Harjani, J Harvey, R Sainati
17th International Conference on VLSI Design. Proceedings., 941-948, 2004
712004
Feasibility and performance region modeling of analog and digital circuits
R Harjani, J Shao
Modeling and Simulation of Mixed Analog-Digital Systems, 23-43, 1996
711996
A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter
K Nair, R Harjani
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC …, 2004
702004
Pulse generator design for UWB IR communication systems
B Jung, YH Tseng, J Harvey, R Harjani
2005 IEEE International Symposium on Circuits and Systems, 4381-4384, 2005
632005
A new noncoherent UWB impulse radio receiver
MK Oh, B Jung, R Harjani, DJ Park
IEEE communications letters 9 (2), 151-153, 2005
632005
The system can't perform the operation now. Try again later.
Articles 1–20