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Nabil Badereddine
Nabil Badereddine
Email verificata su intel.com - Home page
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Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics
N Badereddine, P Girard, S Pravossoudovitch, C Landrault, A Virazel, ...
International Conference on Design and Test of Integrated Systems in …, 2006
682006
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes
RA Fonseca, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Virazel, ...
2010 15th IEEE European Test Symposium, 132-137, 2010
292010
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes
RA Fonseca, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Virazel, ...
2010 15th IEEE European Test Symposium, 132-137, 2010
292010
Scan cell reordering for peak power reduction during scan test cycles
N Badereddine, P Girard, S Pravossoudovitch, A Virazel, C Landrault
Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5 …, 2007
212007
Structural-based power-aware assignment of don't cares for peak power reduction during scan testing
N Badereddine, P Girard, S Pravossoudovitch, C Landrault, A Virazel, ...
2006 IFIP International Conference on Very Large Scale Integration, 403-408, 2006
172006
A selective scan slice encoding technique for test data volume and test power reduction
N Badereddine, Z Wang, P Girard, K Chakrabarty, A Virazel, ...
Journal of electronic testing 24, 353-364, 2008
162008
A statistical simulation method for reliability analysis of SRAM core-cells
RA Fonseca, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Virazel, ...
Proceedings of the 47th Design Automation Conference, 853-856, 2010
142010
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability
EI Vatajelu, A Bosio, L Dilillo, P Girard, A Todri, A Virazel, N Badereddine
2013 18th IEEE European Test Symposium (ETS), 1-6, 2013
132013
Assist circuits for SRAM testing
N Badereddine, LHB Zordan, P Girard, A Bosio
US Patent 9,418,759, 2016
112016
Power-aware test data compression for embedded IP cores
N Badereddine, Z Wang, P Girard, K Chakrabarty, S Pravossoudovitch, ...
2006 15th Asian Test Symposium, 5-10, 2006
112006
Minimizing peak power consumption during scan testing: Structural technique for don't care bits assignment
N Badereddine, P Girard, S Pravossoudovitch, C Landrault, A Virazel, ...
2006 Ph. D. Research in Microelectronics and Electronics, 65-68, 2006
102006
Low-power SRAMs power mode control logic: Failure analysis and test solutions
LB Zordan, A Bosio, L Dilillo, P Girard, A Todri, A Virazel, N Badereddine
2012 IEEE International Test Conference, 1-10, 2012
92012
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures
EI Vatajelu, A Bosio, L Dilillo, P Girard, A Todri, A Virazel, N Badereddine
2013 8th International Conference on Design & Technology of Integrated …, 2013
82013
A 40nm low power SRAM retention circuit with PVT-aware self-refreshing virtual VDD regulation
C Dray, N Badereddine, C Chanussot
2010 IEEE International Memory Workshop, 1-4, 2010
72010
Power-aware scan testing for peak power reduction
N Badereddine, P Girard, S Pravossoudovitch, A Virazel, C Landrault
VLSI-SOC'05: IFIP International Conference on Very Large Scale Integration …, 2005
72005
Detecting NBTI induced failures in SRAM Core-cells
RA Fonseca, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Virazel, ...
2010 28th VLSI Test Symposium (VTS), 75-80, 2010
62010
Impact of resistive-bridging defects in SRAM core-cell
RA Fonseca, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Virazel, ...
2010 Fifth IEEE International Symposium on Electronic Design, Test …, 2010
62010
Peak power consumption during scan testing: Issue, analysis and heuristic solution
N Badereddine, P Girard, S Pravossoudovitch, C Landrault, A Virazel
DDECS'05: IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2005
62005
On the reuse of read and write assist circuits to improve test efficiency in low-power srams
LB Zordan, A Bosio, L Dilillo, P Girard, A Todri, A Virazel, N Badereddine
2013 IEEE International Test Conference (ITC), 1-10, 2013
52013
A built-in scheme for testing and repairing voltage regulators of low-power srams
LB Zordan, A Bosio, L Dilillo, P Girard, A Todri, A Virazel, N Badereddine
2013 IEEE 31st VLSI Test Symposium (VTS), 1-6, 2013
52013
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
Articoli 1–20