Mamata Dalui
Mamata Dalui
Assistant Professor of Department of Computer Science and Engineering, NIT Durgapur
Verified email at cse.nitdgp.ac.in
Title
Cited by
Cited by
Year
Fault tolerant QCA logic design with coupled majority-minority gate
M Dalui, B Sen, BK Sikdar
Int. J. Comput. Appl 1 (29), 81-87, 2010
402010
Characterization of CA rules for SACA targeting detection of faulty nodes in WSN
S Das, NN Naskar, S Mukherjee, M Dalui, BK Sikdar
International Conference on Cellular Automata, 300-311, 2010
272010
Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings
B Sen, M Dalui, BK Sikdar
Proceedings of the International Conference and Workshop on Emerging Trends …, 2010
192010
Design of testable universal logic gate targeting minimum wire-crossings in QCA logic circuit
B Sen, A Sengupta, M Dalui, BK Sikdar
2010 13th Euromicro Conference on Digital System Design: Architectures …, 2010
142010
An efficient test design for cmps cache coherence realizing mesi protocol
M Dalui, BK Sikdar
Progress in VLSI Design and Test, 89-98, 2012
102012
An efficient test design for verification of cache coherence in CMPs
M Dalui, BK Sikdar
2011 IEEE Ninth International Conference on Dependable, Autonomic and Secure …, 2011
92011
A test design for quick determination of incoherency in chip multiprocessors' cache realizing MOESI protocol
M Dalui, BK Sikdar
2012 International Symposium on Electronic System Design (ISED), 216-220, 2012
72012
A cellular automata based test scheme for TSVs in 3D ICs
B Chakraborty, M Dalui
2012 International Conference on Devices, Circuits and Systems (ICDCS), 723-727, 2012
72012
Quick consensus through early disposal of faulty processes
M Dalui, B Chakraborty, BK Sikdar
2009 IEEE International Conference on Systems, Man and Cybernetics, 1989-1994, 2009
72009
A cellular automata based highly accurate memory test hardware realizing March C−
M Saha, M Dalui, BK Sikdar
Microelectronics journal 52, 91-103, 2016
52016
Design of universal logic gate targeting minimum wire-crossings in QCA logic circuit
B Sen, A Sengupta, M Dalui, BK Sikdar
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 1181 …, 2010
52010
Design of a reliable cache system for heterogeneous CMPs
B Chakraborty, M Dalui, BK Sikdar
Journal of Circuits, Systems and Computers 27 (14), 1850219, 2018
42018
A cellular automata based self-correcting protocol processor for scalable CMPs
M Dalui, BK Sikdar
Microelectronics Journal 62, 108-119, 2017
42017
A cache system design for CMPs with built-in coherence verification
M Dalui, BK Sikdar
VLSI Design 2016, 2016
32016
Design of coherence verification unit for heterogeneous CMPs
B Chakraborty, BP Singh, M Chinnapureddy, M Dalui, BK Sikdar
2015 19th International Symposium on VLSI Design and Test, 1-6, 2015
32015
Covid-19 detection on chest x-ray and ct scan images using multi-image augmented deep learning model
K Purohit, A Kesarwani, DR Kisku, M Dalui
BioRxiv, 2020
22020
Evaluation and detection of hardware trojan for real-time many-core systems
S Hazra, JS Sattenapalli, A Roy, M Dalui
2018 8th International Symposium on Embedded Computing and System Design …, 2018
22018
Ca based scalable protocol processor for chip multiprocessors
M Dalui, BK Sikdar
2014 Fifth International Symposium on Electronic System Design, 161-165, 2014
22014
Design of directory based cache coherence protocol verification logic in CMPs around TACA
M Dalui, BK Sikdar
2013 International Conference on High Performance Computing & Simulation …, 2013
22013
A segmented CA based approach to test TSVs in 3D IC
B Chakraborty, M Dalui
2013 4th International Conference on Intelligent Systems, Modelling and …, 2013
22013
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