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Ritchie Zhao
Ritchie Zhao
Microsoft
Verified email at cornell.edu - Homepage
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Cited by
Year
Accelerating binarized convolutional neural networks with software-programmable FPGAs
R Zhao, W Song, W Zhang, T Xing, JH Lin, M Srivastava, R Gupta, ...
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
3782017
Serving dnns in real time at datacenter scale with project brainwave
E Chung, J Fowers, K Ovtcharov, M Papamichael, A Caulfield, ...
iEEE Micro 38 (2), 8-20, 2018
2762018
Improving neural network quantization without retraining using outlier channel splitting
R Zhao, Y Hu, J Dotzel, C De Sa, Z Zhang
International conference on machine learning, 7543-7552, 2019
1842019
The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
912018
Rosetta: A realistic high-level synthesis benchmark suite for software programmable fpgas
Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ...
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
872018
Accelerating persistent neural networks at datacenter scale
E Chung, J Fowers, K Ovtcharov, M Papamichael, A Caulfield, ...
Hot Chips 29, 2017
682017
Elasticflow: A complexity-effective approach for pipelining irregular loop nests
M Tan, G Liu, R Zhao, S Dai, Z Zhang
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 78-85, 2015
552015
A parallel bandit-based approach for autotuning FPGA compilation
C Xu, G Liu, R Zhao, S Yang, G Luo, Z Zhang
Proceedings of the 2017 ACM/SIGDA international symposium on field …, 2017
462017
Pushing the limits of narrow precision inferencing at cloud scale with microsoft floating point
B Darvish Rouhani, D Lo, R Zhao, M Liu, J Fowers, K Ovtcharov, ...
Advances in neural information processing systems 33, 10271-10281, 2020
342020
Dynamic hazard resolution for pipelining irregular loops in high-level synthesis
S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
322017
Binarized convolutional neural networks with separable filters for efficient hardware acceleration
JH Lin, T Xing, R Zhao, Z Zhang, M Srivastava, Z Tu, RK Gupta
Proceedings of the IEEE Conference on Computer Vision and Pattern …, 2017
312017
Celerity: An open source RISC-V tiered accelerator fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
302017
Building efficient deep neural networks with unitary group convolutions
R Zhao, Y Hu, J Dotzel, CD Sa, Z Zhang
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2019
292019
A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
2019 Symposium on VLSI Circuits, C30-C31, 2019
222019
Area-efficient pipelining for FPGA-targeted high-level synthesis
R Zhao, M Tan, S Dai, Z Zhang
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
212015
Precision gating: Improving neural network efficiency with dynamic dual-precision activations
Y Zhang, R Zhao, W Hua, N Xu, GE Suh, Z Zhang
arXiv preprint arXiv:2002.07136, 2020
192020
Improving high-level synthesis with decoupled data structure optimization
R Zhao, G Liu, S Srinath, C Batten, Z Zhang
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
152016
Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019
142019
Enabling adaptive loop pipelining in high-level synthesis
S Dai, G Liu, R Zhao, Z Zhang
2017 51st Asilomar Conference on Signals, Systems, and Computers, 131-135, 2017
132017
Architecture and synthesis for area-efficient pipelining of irregular loop nests
G Liu, M Tan, S Dai, R Zhao, Z Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
122017
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Articles 1–20