Ioannis Seitanidis
Title
Cited by
Cited by
Year
Microarchitecture of Network-on-chip Routers
G Dimitrakopoulos, A Psarras, I Seitanidis
Springer, 2015
532015
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation
A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
312015
Shortpath: A network-on-chip router with fine-grained pipeline bypassing
A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos
IEEE Transactions on Computers 65 (10), 3136-3147, 2016
292016
Elastistore: An elastic buffer architecture for network-on-chip routers
I Seitanidis, A Psarras, G Dimitrakopoulos, C Nicopoulos
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
272014
ElastiStore: Flexible elastic buffering for virtual-channel-based networks on chip
I Seitanidis, A Psarras, K Chrysanthou, C Nicopoulos, G Dimitrakopoulos
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015
192015
ElastiNoC: A self-testable distributed VC-based network-on-chip architecture
I Seitanidis, A Psarras, E Kalligeros, C Nicopoulos, G Dimitrakopoulos
2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 135-142, 2014
172014
PhaseNoC: Versatile network traffic isolation through TDM-scheduled virtual channels
A Psarras, J Lee, I Seitanidis, C Nicopoulos, G Dimitrakopoulos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
162015
Hardware primitives for the synthesis of multithreaded elastic systems
G Dimitrakopoulos, I Seitanidis, A Psarras, K Tsiouris, PM Mattheakis, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
62014
Timing driven incremental multi-bit register composition using a placement-aware ILP formulation
I Seitanidis, G Dimitrakopoulos, P Mattheakis, L Masse-Navette, ...
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
42017
Timing-driven placement optimization facilitated by timing-compatibility flip-flop clustering
D Mangiras, A Stefanidis, I Seitanidis, C Nicopoulos, G Dimitrakopoulos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
32019
Timing-Driven and Placement-Aware Multibit Register Composition
I Seitanidis, G Dimitrakopoulos, PM Mattheakis, L Masse-Navette, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
32018
Automatic generation of peak-power traffic for networks-on-chip
I Seitanidis, C Nicopoulos, G Dimitrakopoulos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
22018
Powermax: An automated methodology for generating peak-power traffic in networks-on-chip
I Seitanidis, C Nicopoulos, G Dimitrakopoulos
2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2016
12016
Low power networks-on-Chip
I Seitanidis
Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Σχολή Πολυτεχνική. Τμήμα Ηλεκτρολόγων …, 2018
2018
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