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Vikas Vijayvargiya
Vikas Vijayvargiya
VIT VILLORE
Verified email at vit.ac.in - Homepage
Title
Cited by
Cited by
Year
Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance
V Vijayvargiya, SK Vishvakarma
IEEE Transactions on Nanotechnology 13 (5), 974-981, 2014
1652014
Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications
V Vijayvargiya, BS Reniwal, P Singh, SK Vishvakarma
Electronics Letters 52 (7), 559-560, 2016
232016
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design
P Singh, BS Reniwal, V Vijayvargiya, V Sharma, SK Vishvakarma
Integration 62, 1-13, 2018
222018
Impact of device engineering on analog/RF performances of tunnel field effect transistors
V Vijayvargiya, BS Reniwal, P Singh, SK Vishvakarma
Semiconductor Science and Technology 32 (6), 065005, 2017
182017
Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry
SK Vishvakarma, A Beohar, V Vijayvargiya, P Trivedi
Journal of Semiconductors 38 (7), 074003, 2017
102017
A new sense amplifier design with improved input referred offset characteristics for energy-efficient SRAM
BS Reniwal, P Singh, V Vijayvargiya, SK Vishvakarma
2017 30th International Conference on VLSI Design and 2017 16th …, 2017
82017
Design of high speed DDR SDRAM controller with less logic utilization
P Singh, B Reniwal, V Vijayvargiya, SK Vishvakarma
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-6, 2014
82014
Ultra-Fast Current Mode Sense Amplifier for Small SRAM in FinFET with Improved Offset Tolerance
BS Reniwal, V Vijayvargiya, SK Vishvakarma, D Dwivedi
Circuits, Systems, and Signal Processing 35 (9), 3066-3085, 2016
62016
Design of resistive load inverter and common source amplifier circuits using symmetric and asymmetric nanowire FETs
VB Sreenivasulu, NA Kumari, V Lokesh, J Ajayan, M Uma, V Vijayvargiya
Journal of Electronic Materials 52 (11), 7268-7279, 2023
42023
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET
BS Reniwal, V Vijayvargiya, P Singh, SK Vishvakarma, D Dwivedi
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 95-98, 2015
42015
Design and implementation of transmission gate based VCO architectures for better performance
ES Jesseca, KKA Majeed, V Vijayvargiya
2022 7th International Conference on Communication and Electronics Systems …, 2022
22022
An auto-calibrated sense amplifier with offset prediction approach for energy-efficient SRAM
BS Reniwal, V Vijayvargiya, P Singh, NK Yadav, SK Vishvakarma, ...
Circuits, Systems, and Signal Processing 38, 1482-1505, 2019
22019
Investigation of DC characteristic on DG-tunnel FET with high-K dielectric using distinct device parameter
S Thakre, A Beohar, V Vijayvargiya, N Yadav, SK Vishvakarma
2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016
22016
Dynamic feedback controlled static random access memory for low power applications
P Singh, BS Reniwal, V Vijayvargiya, V Sharma, SK Vishvakarma
Journal of Low Power Electronics 13 (1), 47-59, 2017
12017
Effect of doping profile on tunneling field effect transistor performance
V Vijayvargiya, S Vishvakarma
2013 Spanish Conference on Electron Devices, 195-198, 2013
12013
Performance Comparison of Nanosheet FET, CombFET and TreeFET: Device and Circuit Perspective
NA Kumari, VB Sreenivasulu, V Vijayvargiya, AK Upadhyay, J Ajayan, ...
IEEE Access, 2024
2024
Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications
NA Kumari, V Vijayvargiya, AK Upadhyay, VB Sreenivasulu, V Narendar, ...
ECS Journal of Solid State Science and Technology 12 (11), 113008, 2023
2023
High performance double gate tunnel field effect transistor for low power applications
V Vijayvargiya, SK Vishvakarma
IN Patent 388,463, 2022
2022
A Comparative Analysis of Machine LearningApproaches to Intrusion Detection
SAI Vikas Vijayvargiya,Akshat Bakliwal, Archit Aggarwal
JOURNAL OF XI'AN UNIVERSITY OF ARCHITECTURE & TECHNOLOGY 13 (9), 229-237, 2021
2021
Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs
N Jagwani, V Vijayvargiya, SK Vishvakarma
2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015
2015
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