Gert Jervan
TitoloCitata daAnno
Test cost minimization for hybrid BIST
G Jervan, Z Peng, R Ubar
Proceedings IEEE International Symposium on Defect and Fault Tolerance in …, 2000
562000
Test time minimization for hybrid BIST of core-based systems
G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin
Journal of Computer Science and Technology 21 (6), 907-912, 2006
472006
High-level and hierarchical test sequence generation
G Jervan, Z Peng, O Goloubeva, MS Reorda, M Violante
Seventh IEEE International High-Level Design Validation and Test Workshop …, 2002
452002
Turbo Tester: a CAD system for teaching digital test
G Jervan, A Markus, P Paomets, J Raik, R Ubar
Microelectronics Education, 287-290, 1998
441998
A hybrid BIST architecture and its optimization for SoC testing
G Jervan, Z Peng, R Ubar, H Kruus
Proceedings International Symposium on Quality Electronic Design, 273-279, 2002
382002
Hybrid BIST time minimization for core-based systems with STUMPS architecture
G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin
Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003
262003
Hybrid BIST optimization using reseeding and test set compaction
G Jervan, E Orasson, H Kruus, R Ubar
Microprocessors and Microsystems 32 (5-6), 254-262, 2008
192008
Fast test cost calculation for hybrid BIST in digital systems
E Orasson, R Raidma, R Ubar, G Jervan, Z Peng
Proceedings Euromicro Symposium on Digital Systems Design, 318-325, 2001
192001
Augmented coaching ecosystem for non-obtrusive adaptive personalized elderly care on the basis of Cloud-Fog-Dew computing paradigm
Y Gordienko, S Stirenko, O Alienin, K Skala, Z Sojat, A Rojbi, JRL Benito, ...
2017 40th International Convention on Information and Communication …, 2017
172017
Energy minimization for hybrid BIST in a system-on-chip test environment
R Ubar, T Shchenova, G Jervan, Z Peng
European Test Symposium (ETS'05), 2-7, 2005
172005
From online fault detection to fault management in Network-on-Chips: A ground-up approach
SP Azad, B Niazmand, K Janson, N George, AS Oyeniran, T Putkaradze, ...
2017 IEEE 20th International Symposium on Design and Diagnostics of …, 2017
132017
Holistic approach for fault-tolerant network-on-chip based many-core systems
SP Azad, B Niazmand, J Raik, G Jervan, T Hollstein
arXiv preprint arXiv:1601.07089, 2016
122016
Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment
Z He, G Jervan, Z Peng, P Eles
8th Euromicro Conference on Digital System Design (DSD'05), 83-86, 2005
122005
A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in noc routers
P Saltarelli, B Niazmand, J Raik, V Govind, T Hollstein, G Jervan, ...
Proceedings of the 9th International Symposium on Networks-on-Chip, 6, 2015
102015
Hierarchical calculation of malicious faults for evaluating the fault-tolerance
R Ubar, S Devadze, M Jenihhin, J Raik, G Jervan, P Ellervee
4th IEEE International Symposium on Electronic Design, Test and Applications …, 2008
102008
Test generation: a hierarchical approach
G Jervan, R Ubar, Z Peng, P Eles
System-level Test and Validation of Hardware/Software Systems, 67-81, 2005
102005
An improved estimation methodology for hybrid BIST cost calculation
G Jervan, Z Peng, R Ubar, O Korelina
Proceedings Norchip Conference, 2004., 297-300, 2004
102004
Logic-based implementation of fault-tolerant routing in 3D network-on-chips
B Niazmand, SP Azad, J Flich, J Raik, G Jervan, T Hollstein
2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2016
92016
Automated minimization of concurrent online checkers for network-on-chips
P Saltarelli, B Niazmand, R Hariharan, J Raik, G Jervan, T Hollstein
2015 10th International Symposium on Reconfigurable Communication-centric …, 2015
92015
Communication modelling and synthesis for NoC-based systems with real-time constraints
M Tagel, P Ellervee, T Hollstein, G Jervan
14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011
92011
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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