| An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications M Kaul, R Vemuri, S Govindarajan, I Ouaiss Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 616-622, 1999 | 171 | 1999 |
| An integrated partitioning and synthesis system for dynamically reconfigurable multi-FPGA architectures I Ouaiss, S Govindarajan, V Srinivasan, M Kaul, R Vemuri Parallel and Distributed Processing, 31-36, 1998 | 128 | 1998 |
| Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers I Ouaiss, R Vemuri Proceedings of the conference on Design, automation and test in Europe, 650-657, 2001 | 47 | 2001 |
| An effective design system for dynamically reconfigurable architectures S Govindarajan, I Ouaiss, M Kaul, V Srinivasan, R Vemuri FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on …, 1998 | 38 | 1998 |
| An effective design approach for dynamically reconfigurable architectures S Govindarajan, I Ouaiss, M Kaul, V Srinivasan, R Vemuri IEEE Symposium on FPGAs for Custom Computing Machines, FCCM’98, 0 | 38* | |
| Register binding for FPGAs with embedded memory HA Atat, I Ouaiss Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual …, 2004 | 27 | 2004 |
| A unified specification model of concurrency and coordination for synthesis from VHDL I Ouaiss, S Govindarajan, V Srinivasan, M Kaul, R Vemuri Proceedings of the 4th International Conference on Information Systems …, 1998 | 21 | 1998 |
| An Automated Temporal Partitioning Tool for a class of DSP applications M Kaul, R Vemuri, S Govindarajan, I Ouaiss Workshop on Reconfigurable Computing in International Conference on Parallel …, 1998 | 19 | 1998 |
| Optimizing register binding in FPGAs using simulated annealing A Avakian, I Ouaiss Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International …, 2005 | 14 | 2005 |
| A novel pseudorandom noise and band jammer generator using a composite sinusoidal function SS Saab, JG Hobeika, IE Ouaiss Signal Processing, IEEE Transactions on 58 (2), 535-543, 2010 | 13 | 2010 |
| Efficient resource arbitration in reconfigurable computing environments I Ouaiss, R Vemuri Proceedings of the conference on Design, automation and test in Europe, 560-566, 2000 | 13 | 2000 |
| Deadline-based connection setup in wavelength-routed WDM networks W Fawaz, I Ouaiss, K Chen, H Perros Computer Networks 54 (11), 1792-1804, 2010 | 12 | 2010 |
| Hierarchical memory synthesis in reconfigurable computers I OUAISS University of Cincinnati, 2002 | 7 | 2002 |
| Global memory mapping for FPGA-based reconfigurable systems I Ouaiss, R Vemuri Proceedings of the 15th International Parallel & Distributed Processing …, 2001 | 6 | 2001 |
| Partitioning and synthesis for run-time reconfigurable computers using the SPARCS system M Kaul, V Srinivasan, S Govindarajan, I Ouaiss, R Vemuri Proceedings of the 1998 Military and Aerospace Applications of Programmable …, 1998 | 6 | 1998 |
| A Comparative Study of Device Driver APIs Towards a Uniform Linux Approach W Zaatar, I Ouaiss Ottawa Linux Symposium, 407, 2002 | 5 | 2002 |
| Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations G Zgheib, I Ouaiss Journal of Circuits, Systems and Computers 24 (03), 1550039, 2015 | 4 | 2015 |
| Automated design synthesis and partitioning for adaptive reconfigurable hardware R Vemuri, S Govindarajan, I Ouaiss, M Kaul, V Srinivasan, ... Hardware implementation of intelligent systems, 3-52, 2001 | 4 | 2001 |
| A Novel Register-Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis E El Aaraj, I Ouaiss Journal of Circuits Systems and Computers 20 (5), 943-973, 2011 | 2 | 2011 |
| Localization of epileptogenic foci using artificial neural networks IE Ouaiss, AP Dhawan, MD Privitera Engineering in Medicine and Biology Society, 1994. Engineering Advances: New …, 1994 | 2 | 1994 |
