Eugenio Dentoni Litta
Citata da
Citata da
Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration
H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ...
2017 IEEE International Electron Devices Meeting (IEDM), 37.4. 1-37.4. 4, 2017
Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors
S Vaziri, M Belete, ED Litta, AD Smith, G Lupina, MC Lemme, M Ístling
Nanoscale 7 (30), 13096-13104, 2015
First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs
E Capogreco, L Witters, H Arimura, F Sebaai, C Porret, A Hikavyy, R Loo, ...
IEEE Transactions on Electron Devices 65 (11), 5145-5150, 2018
Thulium silicate interfacial layer for scalable high-k/metal gate stacks
ED Litta, PE Hellstr÷m, C Henkel, M Ístling
IEEE transactions on electron devices 60 (10), 3271-3276, 2013
High-deposition-rate atomic layer deposition of thulium oxide from TmCp3 and H2O
ED Litta, PE Hellstr÷m, C Henkel, S Valerio, A HallÚn, M Ístling
Journal of the Electrochemical Society 160 (11), D538, 2013
Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology
ED Litta, PE Hellstr÷m, M Ístling
IEEE Transactions on Electron Devices 62 (3), 934-939, 2015
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019
Interface engineering of Ge using thulium oxide: Band line-up study
IZ Mitrovic, M Althobaiti, AD Weerakkody, N Sedghi, S Hall, VR Dhanak, ...
Microelectronic engineering 109, 204-207, 2013
Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology
ED Litta, PE Hellstr÷m, C Henkel, M Ístling
Solid-state electronics 98, 20-25, 2014
Treatments for reliability improvement in thick oxides diffusion and gate replacement I/O transistors
R Ritzenthaler, M Cho, T Schram, A Spessot, E Simoen, BJ O'Sullivan, ...
International Journal of Materials Engineering Innovation 8 (1), 53-70, 2017
In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks
E Dentoni Litta, PE Hellstrom, C Henkel, M Ostling
Ultimate Integration on Silicon (ULIS), 2012 13th International Conferenceá…, 2012
Characteristics of a wire-bonding-less SiC power module operating in a wide temperature range
S Sato, H Tanisawa, T Anzai, H Takahashi, Y Murakami, F Kato, ...
ECS Transactions 69 (11), 123, 2015
Mobility enhancement by integration of TmSiO IL in 0.65 nm EOT high-k/metal gate MOSFETs
ED Litta, PE Hellstr÷m, M Ístling
2013 Proceedings of the European Solid-State Device Research Conferenceá…, 2013
TaN versus TiN metal gate input/output pMOSFETs: A low-frequency noise perspective
E Simoen, B O’sullivan, R Ritzenthaler, ED Litta, T Schram, N Horiguchi, ...
IEEE Transactions on Electron Devices 65 (9), 3676-3681, 2018
Gate stack engineering to enhance high-κ/metal gate reliability for DRAM I/O applications
BJ O'Sullivan, R Ritzenthaler, E Simoen, ED Litta, T Schram, A Chasin, ...
2017 IEEE International Reliability Physics Symposium (IRPS), DG-8.1-DG-8.5, 2017
Enhanced Channel Mobility at Sub-nm EOT by Integration of a TmSiO Interfacial Layer in HfO2/TiN High-k/Metal Gate MOSFETs
ED Litta, PE Hellstr÷m, M Ístling
IEEE Journal of the Electron Devices Society 3 (5), 397-404, 2015
Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs
ED Litta, PE Hellstr÷m, M Ístling
Solid-State Electronics 108, 24-29, 2015
Ultra-thin film and interface analysis of high-k dielectric materials employing Time-Of-Flight Medium Energy Ion Scattering (TOF-MEIS)
D Primetzhofer, ED Litta, A HallÚn, MK Linnarsson, G Possnert
Nuclear Instruments and Methods in Physics Research Section B: Beamá…, 2014
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits
ED Litta, R Ritzenthaler, T Schram, A Spessot, B O’Sullivan, ...
Japanese Journal of Applied Physics 57 (4S), 04FB08, 2018
Il sistema al momento non pu˛ eseguire l'operazione. Riprova pi¨ tardi.
Articoli 1–20