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Eugenio Dentoni Litta
Eugenio Dentoni Litta
Email verificata su imec.be - Home page
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Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration
H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ...
2017 IEEE international electron devices meeting (IEDM), 37.4. 1-37.4. 4, 2017
1182017
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019
892019
First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs
E Capogreco, L Witters, H Arimura, F Sebaai, C Porret, A Hikavyy, R Loo, ...
IEEE Transactions on Electron Devices 65 (11), 5145-5150, 2018
672018
First monolithic integration of 3d complementary fet (cfet) on 300mm wafers
S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ...
2020 Ieee Symposium on Vlsi Technology, 1-2, 2020
592020
Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors
S Vaziri, M Belete, ED Litta, AD Smith, G Lupina, MC Lemme, M Östling
Nanoscale 7 (30), 13096-13104, 2015
592015
Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space
H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ...
2021 Symposium on VLSI Technology, 1-2, 2021
472021
Thulium silicate interfacial layer for scalable high-k/metal gate stacks
ED Litta, PE Hellström, C Henkel, M Östling
IEEE transactions on electron devices 60 (10), 3271-3276, 2013
322013
Buried power rail integration with FinFETs for ultimate CMOS scaling
A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ...
IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020
302020
High-deposition-rate atomic layer deposition of thulium oxide from TmCp3 and H2O
ED Litta, PE Hellström, C Henkel, S Valerio, A Hallén, M Östling
Journal of the Electrochemical Society 160 (11), D538, 2013
242013
Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology
ED Litta, PE Hellström, M Östling
IEEE Transactions on Electron Devices 62 (3), 934-939, 2015
232015
Nanosheet FETs and their potential for enabling continued Moore's law scaling
A Veloso, G Eneman, A De Keersgieter, D Jang, H Mertens, P Matagne, ...
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2021
182021
Comparison of electrical performance of co-integrated forksheets and nanosheets transistors for the 2nm technological node and beyond
R Ritzenthaler, H Mertens, G Eneman, E Simoen, E Bury, P Eyben, ...
2021 IEEE International Electron Devices Meeting (IEDM), 26.2. 1-26.2. 4, 2021
162021
Enabling logic with backside connectivity via n-TSVs and its potential as a scaling booster
A Veloso, A Jourdain, G Hiblot, F Schleicher, K D’have, F Sebaai, ...
2021 Symposium on VLSI Technology, 1-2, 2021
162021
Buried power rail integration with Si FinFETs for CMOS scaling beyond the 5 nm node
A Gupta, H Mertens, Z Tao, S Demuynck, J Bömmels, G Arutchelvan, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
152020
Buried power SRAM DTCO and system-level benchmarking in N3
S Salahuddin, M Perumkunnil, ED Litta, A Gupta, P Weckx, J Ryckaert, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
152020
Interface engineering of Ge using thulium oxide: Band line-up study
IZ Mitrovic, M Althobaiti, AD Weerakkody, N Sedghi, S Hall, VR Dhanak, ...
Microelectronic engineering 109, 204-207, 2013
132013
Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology
ED Litta, PE Hellström, C Henkel, M Östling
Solid-state electronics 98, 20-25, 2014
122014
In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks
E Dentoni Litta, PE Hellstrom, C Henkel, M Ostling
Ultimate Integration on Silicon (ULIS), 2012 13th International Conference …, 2012
12*2012
Process variation analysis of device performance using virtual fabrication: methodology demonstrated on a CMOS 14-nm FinFET vehicle
B Vincent, R Hathwar, M Kamon, J Ervin, T Schram, T Chiarella, ...
IEEE Transactions on Electron Devices 67 (12), 5374-5380, 2020
112020
Forksheet FETs with bottom dielectric isolation, self-aligned gate cut, and isolation between adjacent source-drain structures
H Mertens, R Ritzenthaler, Y Oniki, PP Gowda, G Mannaert, F Sebaai, ...
2022 International Electron Devices Meeting (IEDM), 23.1. 1-23.1. 4, 2022
102022
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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