Austin Rovinski
Austin Rovinski
Verified email at umich.edu - Homepage
Title
Cited by
Cited by
Year
Neurosurgeon: Collaborative intelligence between the cloud and mobile edge
Y Kang, J Hauswald, C Gao, A Rovinski, T Mudge, J Mars, L Tang
ACM SIGARCH Computer Architecture News 45 (1), 615-629, 2017
2852017
Sirius: An open end-to-end voice and vision personal assistant and its implications for future warehouse scale computers
J Hauswald, MA Laurenzano, Y Zhang, C Li, A Rovinski, A Khurana, ...
Proceedings of the Twentieth International Conference on Architectural …, 2015
1992015
The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
292018
Celerity: An open source RISC-V tiered accelerator fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
202017
Designing future warehouse-scale computers for Sirius, an end-to-end voice and vision personal assistant
J Hauswald, MA Laurenzano, Y Zhang, H Yang, Y Kang, C Li, A Rovinski, ...
ACM Transactions on Computer Systems (TOCS) 34 (1), 1-32, 2016
132016
Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm
TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ...
1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
92017
A 7.3 m output non-zeros/j sparse matrix-matrix multiplication accelerator using memory reconfiguration in 40 nm
S Pal, D Park, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ...
2019 Symposium on VLSI Technology, C150-C151, 2019
52019
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator
DH Park, S Pal, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ...
IEEE Journal of Solid-State Circuits 55 (4), 933-944, 2020
42020
Sirius implications for future warehouse-scale computers
J Hauswald, MA Laurenzano, Y Zhang, C Li, A Rovinski, A Khurana, ...
IEEE Micro 36 (3), 42-53, 2016
42016
OpenROAD: Toward a self-driving, open-source digital layout implementation tool chain
T Ajayi, D Blaauw
Proceedings of Government Microcircuit Applications and Critical Technology …, 2019
32019
A carbon nanotube transistor based RISC-V processor using pass transistor logic
A Amarnath, S Feng, S Pal, T Ajayi, A Rovinski, RG Dreslinski
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
32017
A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
2019 Symposium on VLSI Circuits, C30-C31, 2019
22019
Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices
X He, S Pal, A Amarnath, S Feng, DH Park, A Rovinski, H Ye, Y Chen, ...
International Conference on Supercomputing (ICS’20), 2020
12020
Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019
2019
Neurosurgeon
Y Kang, J Hauswald, C Gao, A Rovinski, T Mudge, J Mars, L Tang
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