| AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement I Alouani, WM Elsharkasy, AM Eltawil, FJ Kurdahi, S Niar IET Circuits, Devices & Systems 11 (1), 89-94, 2017 | 39 | 2017 |
| A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET RL Nguyen, AM Castrillon, A Fan, A Mellati, BT Reyes, C Abidin, E Olsen, ... IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers 64, 136-138, 2021 | 33 | 2021 |
| NUVA: architectural support for runtime verification of parametric specifications over multicores A Nassar, FJ Kurdahi, W Elsharkasy Proceedings of the 2015 International Conference on Compilers, Architecture …, 2015 | 21 | 2015 |
| 8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET RL Nguyen, AM Castrillon, A Fan, A Mellati, BT Reyes, C Abidin, E Olsen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 136-138, 2021 | 19 | 2021 |
| Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches WM Elsharkasy, A Khajeh, AM Eltawil, FJ Kurdahi IEEE Transactions on Circuits and Systems I: Regular Papers, 2017 | 14 | 2017 |
| Efficient pulsed-latch implementation for multiport register files: work-in-progress WM Elsharkasy, HE Yantir, A Khajeh, AM Eltawil, FJ Kurdahi Proceedings of the 2017 International Conference on Compilers, Architectures …, 2017 | 3 | 2017 |
| Low overhead correction scheme for unreliable LDPC buffering AM Hussien, WM Elsharkasy, AM Eltawil, F Kurdahi, A Khajeh Global Conference on Signal and Information Processing (GlobalSIP), 2013 …, 2013 | 3 | 2013 |
| Low Power Reliable Design using Pulsed Latch Circuits WM Elsharkasy | 2 | 2017 |
| FPGA implementation of high speed XTS-AES for data storage devices M Elmoghany, M Diab, M Kassem, M Khairallah, O El Shahat, W Sharkasy Internet Technology and Secured Transactions (ICITST), 2011 International …, 2011 | 2 | 2011 |
| 18.4 A 200GS/s 8b 20fJ/cs Receiver with> 60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET RL Nguyen, A Mellati, A Fernandez, A Iyer, A Fan, B Reyes, C Abidin, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 344-346, 2024 | 1 | 2024 |
| Hardware modelling of JPEG2000 MQ-encoder WM El-Sharkasy, ME Ragab Intelligent and Advanced Systems (ICIAS), 2012 4th International Conference …, 2012 | 1 | 2012 |
| 18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm F Ahmad, A Mellati, A Fernandez, A Iyer, A Fan, B Reyes, C Abidin, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 342-344, 2024 | | 2024 |
| AS8-SRAM: Asymmetric SRAM Architecture For Soft Error Hardening Enhancement I Alouani, WM Elsharkasy, AM Eltawil, FJ Kurdahi, S Niar | | |
| Runtime Verification (RV) has recently emerged as a complementary technology to extend coverage of conventional software verification methods. To address the substantial … A Nassar, FJ Kurdahi, W Elsharkasy | | |
