| Modelling the ARMv8 architecture, operationally: Concurrency and ISA S Flur, KE Gray, C Pulte, S Sarkar, A Sezgin, L Maranget, W Deacon, ... Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of …, 2016 | 196 | 2016 |
| Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8 C Pulte, S Flur, W Deacon, J French, S Sarkar, P Sewell Proceedings of the ACM on Programming Languages 2 (POPL), 1-29, 2017 | 186 | 2017 |
| ISA Semantics for ARMv8-a, RISC-v, and CHERI-MIPS A Armstrong, T Bauereiss, B Campbell, A Reid, KE Gray, RM Norton, ... Proceedings of the ACM on Programming Languages 3 (POPL), 1-31, 2019 | 163 | 2019 |
| Mixed-size concurrency: ARM, Power, C/C++ 11, and SC S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ... ACM SIGPLAN Notices 52 (1), 429-442, 2017 | 55 | 2017 |
| Termination proofs for linear simple loops HY Chen, S Flur, S Mukhopadhyay International Journal on Software Tools for Technology Transfer 17, 47-57, 2015 | 41 | 2015 |
| Repairing and mechanising the JavaScript relaxed memory model C Watt, C Pulte, A Podkopaev, G Barbier, S Dolan, S Flur, ... Proceedings of the 41st ACM SIGPLAN Conference on Programming Language …, 2020 | 27 | 2020 |
| Towards making formal methods normal: meeting developers where they are A Reid, L Church, S Flur, S de Haas, M Johnson, B Laurie arXiv preprint arXiv:2010.16345, 2020 | 24 | 2020 |
| ARMv8-A system semantics: instruction fetch in relaxed architectures B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ... Programming Languages and Systems: 29th European Symposium on Programming …, 2020 | 20 | 2020 |
| Formal verification of models using concurrent model-reduction and model-checking E Arbel, S Flur, Z Nevo, M Shamis US Patent 8,244,516, 2012 | 12 | 2012 |
| Detailed models of instruction set architectures: From pseudocode to formal semantics A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, P Mundkur, ... Proceedings of the Automated Reasoning Workshop, 2018 | 11 | 2018 |
| Assertion based verification of multiple-clock gals systems R Dobkin, T Kapshitz, S Flur, R Ginosar Proc. IFIP/IEEE Int. Conference on Very Large Scale Integration (VLSI-SoC), 2008 | 11 | 2008 |
| The Sail instruction-set semantics specification language KE Gray, P Sewell, C Pulte, S Flur, R Norton-Wright Technical report, Cambridge University, 2017. 86 BIBLIOGRAPHY, 2017 | 8 | 2017 |
| Formal verification of models using concurrent model-reduction and model-checking E Arbel, S Flur, Z Nevo, M Shamis US Patent 8,417,507, 2013 | 6 | 2013 |
| Model checking of liveness property in a phase abstracted model JR Baumgartner, S Flur, Z Nevo, PJ Roessler US Patent 8,627,273, 2014 | 5 | 2014 |
| The state of sail A Armstrong, T Bauereiss, B Campbell, A Reid, KE Gray, R Norton, ... SpISA 2019: Workshop on Instruction Set Architecture Specification, 2019 | 4 | 2019 |
| The Sail instruction-set semantics specification language A Armstrong, T Bauereiss, B Campbell, KE Gray, R Norton-Wright, C Pulte, ... | 2 | 2021 |
| Detection of design redundancy S Flur, Z Nevo US Patent 8,554,522, 2013 | 2 | 2013 |
| Research data supporting “Mixed-size Concurrency: ARM, POWER, C/C++ 11, and SC” S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ... University of Cambridge, 2016 | | 2016 |
| An Axiomatic Semantics for Instruction Fetching B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ... | | |
| Reduction Assistant: Model Reduction in Parallel with Model Checking E Arbel, S Flur, Z Nevo, S Ruah, M Shamis | | |
