Adrià Armejach
Adrià Armejach
Juan de la Cierva Fellow at UPC and Associate Researcher at BSC
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Cited by
EazyHTM: Eager-lazy hardware transactional memory
S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ...
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
An empirical evaluation of high-level synthesis languages and tools for database acceleration
O Arcas-Abella, G Ndu, N Sonmez, M Ghasempour, A Armejach, ...
2014 24th International Conference on Field Programmable Logic and …, 2014
MUSA: a multi-level simulation approach for next-generation HPC machines
T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ...
SC'16: Proceedings of the International Conference for High Performance …, 2016
Using Arm’s scalable vector extension on stencil codes
A Armejach, H Caminal, JM Cebrian, R Langarita, R González-Alberquilla, ...
The Journal of Supercomputing 76, 2039-2062, 2020
Stencil codes on a vector length agnostic architecture
A Armejach, H Caminal, JM Cebrian, R González-Alberquilla, ...
Proceedings of the 27th International Conference on Parallel Architectures …, 2018
Using a reconfigurable L1 data cache for efficient version management in hardware transactional memory
A Armejach, A Seyedi, R Titos-Gil, I Hur, OS Unsal, M Valero
2011 International Conference on Parallel Architectures and Compilation …, 2011
HARP: Adaptive abort recurrence prediction for hardware transactional memory
A Armejach, A Negi, A Cristal, O Unsal, P Stenstrom, T Harris
20th Annual International Conference on High Performance Computing, 196-205, 2013
Hardware acceleration for query processing: leveraging FPGAs, CPUs, and memory
O Arcas-Abella, A Armejach, T Hayes, GA Malazgirt, O Palomar, B Salami, ...
Computing in Science & Engineering 18 (1), 80-87, 2015
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
A Seyedi, A Armejach, A Cristal, OS Unsal, I Hur, M Valero
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
Techniques to improve performance in requester-wins hardware transactional memory
A Armejach, R Titos-Gil, A Negi, OS Unsal, A Cristal
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-25, 2013
Design space exploration of next-generation HPC machines
C Gómez, F Martınez, A Armejach, M Moretó, F Mantovani, M Casas
2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019
Implications of non-volatile memory as primary storage for database management systems
NU Mustafa, A Armejach, O Ozturk, A Cristal, OS Unsal
2016 International Conference on Embedded Computer Systems: Architectures …, 2016
On the use of many-core Marvell ThunderX2 processor for HPC workloads
V Soria-Pardos, A Armejach, D Suárez, M Moretó
The Journal of Supercomputing 77, 3315-3338, 2021
Towards resilient EU HPC systems: A blueprint
P Radojkovic, M Marazakis, P Carpenter, R Jeyapaul, D Gizopoulos, ...
European HPC resilience initiative, 2020
Evaluating mixed-precision arithmetic for 3D generative adversarial networks to simulate high energy physics detectors
JO Ríos, A Armejach, G Khattak, E Petit, S Vallecorsa, M Casas
2020 19th IEEE International Conference on Machine Learning and Applications …, 2020
Compressed sparse FM-index: Fast sequence alignment using large k-steps
R Langarita, A Armejach, J Setoain, P Ibanez-Marin, J Alastruey-Benedé, ...
IEEE/ACM Transactions on Computational Biology and Bioinformatics 19 (1 …, 2020
gem5+ rtl: A Framework to Enable RTL Models Inside a Full-System Simulator
G López-Paradís, A Armejach, M Moretó
50th International Conference on Parallel Processing, 1-11, 2021
Dynamically adapting floating-point precision to accelerate deep neural network training
JO Ríos, A Armejach, E Petit, G Henry, M Casas
2021 20th IEEE International Conference on Machine Learning and Applications …, 2021
Novel SRAM bias control circuits for a low power L1 data cache
A Seyedi, A Armejach, A Cristal, OS Unsal, M Valero
NORCHIP 2012, 1-6, 2012
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