| Design and safety verification of a distributed charge equalizer for modular li-ion batteries F Baronti, C Bernardeschi, L Cassano, A Domenici, R Roncella, R Saletti IEEE Transactions on Industrial Informatics 10 (2), 1003-1011, 2014 | 65 | 2014 |
| SRAM-based FPGA systems for safety-critical applications: A survey on design standards and proposed methodologies C Bernardeschi, L Cassano, A Domenici Journal of Computer Science and Technology 30, 373-390, 2015 | 47 | 2015 |
| Accurate Simulation of SEUs in the Configuration Memory of SRAM-based FPGAs C Bernardeschi, L Cassano, A Domenici, L Sterpone The 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2012 | 40 | 2012 |
| Fast and accurate error simulation for cnns against soft errors C Bolchini, L Cassano, A Miele, A Toschi IEEE Transactions on Computers 72 (4), 984-997, 2022 | 26 | 2022 |
| ASSESS: A simulator of soft errors in the configuration memory of SRAM-based FPGAs C Bernardeschi, L Cassano, A Domenici, L Sterpone IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 26 | 2014 |
| GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs C Bernardeschi, L Cassano, MGCA Cimino, A Domenici Journal of Systems Architecture 59 (10), 1243-1254, 2013 | 22 | 2013 |
| A methodology for the design and deployment of distributed cyber–physical systems for smart environments G Tanganelli, L Cassano, A Miele, C Vallati Future generation computer systems 109, 420-430, 2020 | 21 | 2020 |
| A neural network based fault management scheme for reliable image processing M Biasielli, C Bolchini, L Cassano, E Koyuncu, A Miele IEEE Transactions on Computers 69 (5), 764-776, 2020 | 21 | 2020 |
| Failure probability of SRAM-FPGA systems with Stochastic Activity Networks C Bernardeschi, L Cassano, A Domenici 14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011 | 20 | 2011 |
| Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis C Bolchini, L Cassano, A Miele 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 804-809, 2016 | 19 | 2016 |
| A microprocessor protection architecture against hardware trojans in memories A Bolat, L Cassano, P Reviriego, O Ergin, M Ottavi 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 1-6, 2020 | 17 | 2020 |
| Processor security: Detecting microarchitectural attacks via count-min sketches K Arıkan, A Palumbo, L Cassano, P Reviriego, S Pontarelli, G Bianchi, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (7), 938-951, 2022 | 15 | 2022 |
| SEU-X: a SEu Un-eXcitability prover for SRAM-FPGAs C Bernardeschi, L Cassano, A Domenici The 18th IEEE International On-Line Testing Symposium, 2012 | 15 | 2012 |
| Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs C Bernardeschi, L Cassano, A Domenici, L Sterpone Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 14 | 2013 |
| Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer A Palumbo, L Cassano, B Luzzi, JA Hernández, P Reviriego, G Bianchi, ... Journal of Systems Architecture 128, 102543, 2022 | 13 | 2022 |
| A lightweight security checking module to protect microprocessors against hardware trojan horses A Palumbo, L Cassano, P Reviriego, G Bianchi, M Ottavi 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021 | 12 | 2021 |
| Selective hardening of cnns based on layer vulnerability estimation C Bolchini, L Cassano, A Miele, A Nazzari 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2022 | 11 | 2022 |
| Approximation-based fault tolerance in image processing applications M Biasielli, C Bolchini, L Cassano, A Mazzeo, A Miele IEEE Transactions on Emerging Topics in Computing 10 (2), 648-661, 2021 | 11 | 2021 |
| Optimizing the use of behavioral locking for high-level synthesis C Pilato, L Collini, L Cassano, D Sciuto, S Garg, R Karri IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 10 | 2022 |
| AENEAS: An energy-aware simulator of automatic weather stations D Cesarini, L Cassano, M Kuri, V Bilas, M Avvenuti Ieee sensors journal 14 (11), 3932-3943, 2014 | 10 | 2014 |
cinzia bernardeschiDepartment of Information Engineering, University of PisaVerified email at unipi.it
