| A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ... 2014 IEEE international electron devices meeting, 3.7. 1-3.7. 3, 2014 | 753 | 2014 |
| 13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V … P Jain, U Arslan, M Sekhar, BC Lin, L Wei, T Sahu, J Alzate-Vinasco, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 212-214, 2019 | 134 | 2019 |
| A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches KC Chun, P Jain, JH Lee, CH Kim IEEE Journal of Solid-State Circuits 46 (6), 1495-1505, 2011 | 132 | 2011 |
| 13.3 a 7mb stt-mram in 22ffl finfet technology with 4ns read sensing time at 0.9 v using write-verify-write scheme and offset-cancellation sensing technique L Wei, JG Alzate, U Arslan, J Brockman, N Das, K Fischer, T Ghani, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 214-216, 2019 | 131 | 2019 |
| A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches KC Chun, P Jain, TH Kim, CH Kim IEEE Journal of Solid-State Circuits 47 (2), 547-559, 2011 | 110 | 2011 |
| 16.2 eDRAM-CIM: Compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing S Xie, C Ni, A Sayal, P Jain, F Hamzaoglu, JP Kulkarni 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 248-250, 2021 | 86 | 2021 |
| A multi-story power delivery technique for 3D integrated circuits P Jain, TH Kim, J Keane, CH Kim Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | 81 | 2008 |
| Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing K Fischer, M Agostinelli, C Allen, D Bahr, M Bost, P Charvat, ... 2015 IEEE International Interconnect Technology Conference and 2015 IEEE …, 2015 | 78 | 2015 |
| Non-volatile RRAM embedded into 22FFL FinFET technology O Golonzka, U Arslan, P Bai, M Bohr, O Baykan, Y Chang, A Chaudhari, ... 2019 Symposium on VLSI Technology, T230-T231, 2019 | 65 | 2019 |
| A 2T1C embedded DRAM macro with no boosted supplies featuring a 7T SRAM based repair and a cell storage monitor KC Chun, W Zhang, P Jain, CH Kim IEEE journal of solid-state circuits 47 (10), 2517-2526, 2012 | 58 | 2012 |
| A sub-0.9 V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias KC Chun, P Jain, JH Lee, CH Kim 2009 Symposium on VLSI Circuits, 134-135, 2009 | 54 | 2009 |
| Silicon odometers: Compact in situ aging sensors for robust system design X Wang, J Keane, TTH Kim, P Jain, Q Tang, CH Kim IEEE micro 34 (6), 74-85, 2014 | 41 | 2014 |
| Thermal and power delivery challenges in 3D ICs P Jain, P Zhou, CH Kim, SS Sapatnekar Three Dimensional Integrated Circuit Design: EDA, Design and …, 2010 | 39 | 2010 |
| A 1.1 V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110µsec KC Chun, P Jain, TH Kim, CH Kim 2010 Symposium on VLSI Circuits, 191-192, 2010 | 34 | 2010 |
| A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies KC Chun, W Zhang, P Jain, CH Kim 2011 IEEE International Solid-State Circuits Conference, 506-507, 2011 | 22 | 2011 |
| Gain-cell CIM: Leakage and bitline swing aware 2T1C gain-cell eDRAM compute in memory design with bitline precharge DACs and compact Schmitt trigger ADCs S Xie, C Ni, P Jain, F Hamzaoglu, JP Kulkarni 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 17 | 2022 |
| Duty-cycle shift under asymmetric BTI aging: A simple characterization method and its application to SRAM timing X Wang, J Keane, P Jain, V Reddy, CH Kim 2013 IEEE International Reliability Physics Symposium (IRPS), 4A. 5.1-4A. 5.5, 2013 | 17 | 2013 |
| Impact of interconnect length on BTI and HCI induced frequency degradation X Wang, P Jain, D Jiao, CH Kim 2012 IEEE International Reliability Physics Symposium (IRPS), 2F. 5.1-2F. 5.6, 2012 | 17 | 2012 |
| The dependence of BTI and HCI-induced frequency degradation on interconnect length and its circuit level implications X Wang, Q Tang, P Jain, D Jiao, CH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 280-291, 2014 | 16 | 2014 |
| A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI P Jain, A Paul, X Wang, CH Kim 2012 International Electron Devices Meeting, 9.7. 1-9.7. 4, 2012 | 15 | 2012 |
Ki Chul ChunSamsung ElectronicsEmail verificata su samsung.com
