Pulkit Jain
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Citata da
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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 m2SRAM cell size
S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ...
2014 IEEE International Electron Devices Meeting, 3.7. 1-3.7. 3, 2014
5222014
A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches
KC Chun, P Jain, JH Lee, CH Kim
IEEE Journal of Solid-State Circuits 46 (6), 1495-1505, 2011
1042011
A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches
KC Chun, P Jain, TH Kim, CH Kim
IEEE Journal of Solid-State Circuits 47 (2), 547-559, 2011
862011
A multi-story power delivery technique for 3D integrated circuits
P Jain, TH Kim, J Keane, CH Kim
Proceeding of the 13th international symposium on Low power electronics and…, 2008
782008
Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing
K Fischer, M Agostinelli, C Allen, D Bahr, M Bost, P Charvat, ...
2015 IEEE International Interconnect Technology Conference and 2015 IEEE…, 2015
512015
A sub-0.9 V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias
KC Chun, P Jain, JH Lee, CH Kim
2009 Symposium on VLSI Circuits, 134-135, 2009
512009
A 2T1C embedded DRAM macro with no boosted supplies featuring a 7T SRAM based repair and a cell storage monitor
KC Chun, W Zhang, P Jain, CH Kim
IEEE journal of solid-state circuits 47 (10), 2517-2526, 2012
492012
13.3 A 7Mb STT-MRAM in 22FFL FinFET technology with 4ns read sensing time at 0.9 V using write-verify-write scheme and offset-cancellation sensing technique
L Wei, JG Alzate, U Arslan, J Brockman, N Das, K Fischer, T Ghani, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 214-216, 2019
482019
Silicon odometers: Compact in situ aging sensors for robust system design
X Wang, J Keane, TTH Kim, P Jain, Q Tang, CH Kim
IEEE micro 34 (6), 74-85, 2014
332014
Thermal and power delivery challenges in 3D ICs
P Jain, P Zhou, CH Kim, SS Sapatnekar
Three Dimensional Integrated Circuit Design, 33-61, 2010
322010
13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V…
P Jain, U Arslan, M Sekhar, BC Lin, L Wei, T Sahu, J Alzate-vinasco, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 212-214, 2019
302019
A 1.1 V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110sec
KC Chun, P Jain, TH Kim, CH Kim
2010 Symposium on VLSI Circuits, 191-192, 2010
282010
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies
KC Chun, W Zhang, P Jain, CH Kim
2011 IEEE International Solid-State Circuits Conference, 506-507, 2011
212011
Non-volatile RRAM embedded into 22FFL FinFET technology
O Golonzka, U Arslan, P Bai, M Bohr, O Baykan, Y Chang, A Chaudhari, ...
2019 Symposium on VLSI Technology, T230-T231, 2019
142019
Duty-cycle shift under asymmetric BTI aging: A simple characterization method and its application to SRAM timing
X Wang, J Keane, P Jain, V Reddy, CH Kim
2013 IEEE International Reliability Physics Symposium (IRPS), 4A. 5.1-4A. 5.5, 2013
142013
Impact of interconnect length on BTI and HCI induced frequency degradation
X Wang, P Jain, D Jiao, CH Kim
2012 IEEE International Reliability Physics Symposium (IRPS), 2F. 5.1-2F. 5.6, 2012
142012
A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI
P Jain, A Paul, X Wang, CH Kim
2012 International Electron Devices Meeting, 9.7. 1-9.7. 4, 2012
122012
Measurement, analysis and improvement of supply noise in 3D ICs
P Jain, D Jiao, X Wang, CH Kim
2011 Symposium on VLSI Circuits-Digest of Technical Papers, 46-47, 2011
122011
Generic graduate attributes: a research based framework for a shared vision
SC Barrie, P Jain, A Carew
Staff and Educational Development International, 191-199, 2003
122003
An array-based circuit for characterizing latent Plasma-Induced Damage
WH Choi, P Jain, CH Kim
2013 IEEE International Reliability Physics Symposium (IRPS), 4A. 3.1-4A. 3.4, 2013
112013
Il sistema al momento non pu eseguire l'operazione. Riprova pi tardi.
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