| A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications V Sharma, M Gopal, P Singh, SK Vishvakarma, SS Chouhan Analog Integrated Circuits and Signal Processing, Springer, 2018 | 49 | 2018 |
| A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes V Sharma, S Vishvakarma, SS Chouhan, K Halonen International Journal of Circuit Theory and Applications (Wiley) 46 (12 …, 2018 | 46 | 2018 |
| A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications V Sharma, M Gopal, P Singh, SK Vishvakarma AEU-International Journal of Electronics and Communications (Elsevier) 87 …, 2018 | 33 | 2018 |
| Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications V Sharma, P Bisht, A Dalal, M Gopal, SK Vishvakarma, SS Chouhan AEU-International Journal of Electronics and Communications 104, 10-22, 2019 | 32 | 2019 |
| A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes V Sharma, N Gupta, AP Shah, SK Vishvakarma, SS Chouhan Analog Integrated Circuits and Signal Processing 107 (2), 339-352, 2021 | 25 | 2021 |
| Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design P Singh, BS Reniwal, V Vijayvargiya, V Sharma, SK Vishvakarma Integration (Elsevier) 62, 1-13, 2018 | 22 | 2018 |
| Design of low-power CMOS cell structures using subthreshold conduction region V Sharma, S Kumar International journal of scientific and engineering research 2 (2), 29-34, 2011 | 17 | 2011 |
| A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices V Sharma, JE Kim, H Kim, L Lu, TTH Kim IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022 | 15 | 2022 |
| AND8T SRAM Macro with Improved Linearity for Multi-bit In-Memory Computing V Sharma, JE Kim, YJ Jo, Y Chen, TTH Kim 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 15 | 2021 |
| A 64 Kb reconfigurable full-precision digital ReRAM-based compute-in-memory for artificial intelligence applications V Sharma, H Kim, TTH Kim IEEE Transactions on Circuits and Systems I: Regular Papers 69 (8), 3284-3296, 2022 | 12 | 2022 |
| An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application N Gupta, V Sharma, AP Shah, S Khan, M Huebner, SK Vishvakarma International Journal of Numerical Modelling: Electronic Networks, Devices …, 2020 | 11 | 2020 |
| Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit AP Shah, D Rossi, V Sharma, SK Vishvakarma, M Waltl Microelectronics Reliability 107, 113617, 2020 | 11 | 2020 |
| Power reduction in digital VLSI circuits A Dhanotiya, V Sharma International Journal of Research in IT, Management and Engineering 4 (6), 13-23, 2014 | 9 | 2014 |
| ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology L Lu, JE Kim, V Sharma, TTH Kim 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 213-216, 2020 | 8 | 2020 |
| A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture G Raut, AP Shah, V Sharma, G Rajput, SK Vishvakarma Circuits, Systems, and Signal Processing 39 (9), 4681-4694, 2020 | 8 | 2020 |
| Low-Power 1-bit CMOS Full Adder Using Subthreshold Conduction Region V Sharma, S Kumar International Journal of Scientific & Engineering Research 2 (6), 1-6, 2011 | 8 | 2011 |
| Nanoscale memory design for efficient computation: Trends, challenges and opportunity SK Vishvakarma, BS Reniwal, V Sharma, CB Khuswah, D Dwivedi 2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015 | 7 | 2015 |
| Evaluation of static noise margin of 6T SRAM cell using SiGe/SiC asymmetric dual-k spacer FinFETs M Gopal, V Sharma, SK Vishvakarma Micro & Nano Letters 12 (12), 1028-1032, 2017 | 6 | 2017 |
| A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design V Sharma, P Bisht, A Dalal, SS Chouhan, HS Jattana, SK Vishvakarma International Symposium on VLSI Design and Test (Springer), 551-564, 2018 | 5 | 2018 |
| Designing of Low-Power VLSI Circuits using Non-Clocked Logic Style V Sharma, JK Srivastava International Journal of Advancements in Research & Technology (IJOART) 1 (3 …, 2012 | 2 | 2012 |
Dr. Santosh Kumar VishvakarmaIndian Institute of Technology IndoreVerified email at iiti.ac.in
