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Jonathan Rose
Jonathan Rose
Professor of Electrical and Computer Engineering, University of Toronto
Verified email at ece.utoronto.ca - Homepage
Title
Cited by
Cited by
Year
Measuring the gap between FPGAs and ASICs
I Kuon, J Rose
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field …, 2006
18372006
Architecture and CAD for deep-submicron FPGAs
V Betz, J Rose, A Marquardt
Springer Science & Business Media, 1999
1797*1999
VPR: A new packing, placement and routing tool for FPGA research
V Betz, J Rose
International Workshop on Field Programmable Logic and Applications, 213-222, 1997
15611997
Field-Programmable Gate Arrays
S Brown, R Francis, J Rose, Z Vranesic
Kluwer/Springer, ISBN 978-0-7923-9248-4, 1992
1372*1992
FPGA architecture: Survey and challenges
I Kuon, R Tessier, J Rose
Foundations and Trends® in Electronic Design Automation 2 (2), 135-253, 2008
9182008
FPGA and CPLD architectures: A tutorial
S Brown, J Rose
IEEE design & test of computers 13 (2), 42-57, 1996
871*1996
The effect of LUT and cluster size on deep-submicron FPGA performance and density
E Ahmed, J Rose
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field …, 2000
8082000
Architecture of field-programmable gate arrays
J Rose, A El Gamal, A Sangiovanni-Vincentelli
Proceedings of the IEEE 81 (7), 1013-1029, 1993
5341993
VTR 7.0: Next generation architecture and CAD system for FPGAs
J Luu, J Goeders, M Wainberg, A Somerville, T Yu, K Nasartschuk, M Nasr, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-30, 2014
4602014
Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency
J Rose, RJ Francis, D Lewis, P Chow
IEEE Journal of Solid-State Circuits 25 (5), 1217-1225, 1990
4511990
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
R Francis, J Rose, Z Vranesic
Proceedings of the 28th ACM/IEEE design automation conference, 227-233, 1991
3671991
The VTR project: architecture and CAD for FPGAs from verilog to routing
J Rose, J Luu, CW Yu, O Densmore, J Goeders, A Somerville, KB Kent, ...
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
3652012
Timing-driven placement for FPGAs
A Marquardt, V Betz, J Rose
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field …, 2000
3632000
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
A Marquardt, V Betz, J Rose
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999
3631999
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
J Luu, I Kuon, P Jamieson, T Campbell, A Ye, WM Fang, K Kent, J Rose
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (4), 1-23, 2011
3432011
Flexibility of interconnection structures for field-programmable gate arrays
J Rose, S Brown
IEEE Journal of Solid-State Circuits 26 (3), 277-282, 1991
3221991
Chortle: A technology mapping program for lookup table-based field programmable gate arrays
RJ Francis, J Rose, K Chung
Proceedings of the 27th ACM/IEEE Design Automation Conference, 613-619, 1991
2721991
The Stratix II logic and routing architecture
D Lewis, E Ahmed, G Baeckler, V Betz, M Bourgeault, D Cashman, ...
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field …, 2005
2612005
FPGA routing architecture: Segmentation and buffering to optimize speed and density
V Betz, J Rose
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999
2491999
A detailed router for field-programmable gate arrays
S Brown, J Rose, ZG Vranesic
IEEE transactions on computer-aided design of integrated circuits and …, 1992
2451992
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