| A 950 MHz clock 47.5 MHz BW 4.7 mW 67 dB SNDR discrete time delta sigma ADC leveraging ring amplification and split-source comparator based quantizer in 28 nm CMOS LM Santana, E Martens, J Lagos, B Hershberg, P Wambacq, J Craninckx IEEE Journal of Solid-State Circuits 57 (7), 2068-2077, 2022 | 7 | 2022 |
| A 47.5 MHz BW 4.7 mW 67dB SNDR ringamp based discrete-time delta sigma ADC LM Santana, E Martens, J Lagos, B Hershberg, P Wambacq, J Craninckx ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 3 | 2021 |
| A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption HA Delsoto, DL Oliveira, L Santana, LA Faria 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 3 | 2018 |
| A 1V 5-bits Low Power Level Crossing ADC with OFF state in idle time for bio-medical applications in 0.18 um CMOS L Moura Santana, D Lopes de Oliveira, L de Abreu Faria arXiv e-prints, arXiv: 2108.07564, 2021 | 1* | 2021 |
| FPGA implementation of high-performance asynchronous pipelines with robust control DL Oliveira, K Garcia, L Santana, LA Faria 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 1 | 2018 |
| A novel state assignment method for XBM AFSMs without the essential hazard assumption DL Oliveira, T Curtinhas, LM Santana, LA Faria 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018 | 1 | 2018 |
| A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS LM Santana, E Martens, J Lagos, P Wambacq, J Craninckx ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC …, 2023 | | 2023 |
| A technique to enable frequency dependent power savings in a level crossing analog-to-digital converter L Moura Santana, D Lopes de Oliveira, L de Abreu Faria arXiv e-prints, arXiv: 2108.07566, 2021 | | 2021 |
Lester FariaInstituto Tecnológico de Aeronáutica - ITAEmail verificata su ieee.org
