Harald Vranken
Harald Vranken
Open Universiteit & Radboud Universiteit
Verified email at ou.nl
Cited by
Cited by
Sustainability of bitcoin and blockchains
H Vranken
Current opinion in environmental sustainability 28, 1-9, 2017
TriMedia CPU64 architecture
JTJ van Eijndhoven, FW Sijstermans, KA Vissers, EJD Pol, MIA Tromp, ...
Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999
X-masking during logic BIST and its impact on defect coverage
Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ...
2004 International Conferce on Test, 442-451, 2004
Application of deterministic logic BIST on industrial circuits
G Kiefer, H Vranken, EJ Marinissen, HJ Wunderlich
Journal of Electronic Testing 17 (3), 351-362, 2001
Enhanced reduced pin-count test for full-scan design
H Vranken, T Waayers, H Fleury, D Lelouvier
Journal of Electronic Testing 18 (2), 129-143, 2002
Efficient pattern mapping for deterministic logic BIST
V Gherman, HJ Wunderlich, H Vranken, F Hapke, M Wittke, M Garbers
2004 International Conferce on Test, 48-56, 2004
ATPG padding and ATE vector repeat per port for reducing test data volume
H Vranken, F Hapke, S Rogge, D Chindamo, E Volkerink
ITC 3, 1069, 2003
Design for testability in hardware software systems
HPE Vranken, MF Witteman, RC Van Wuijtswinkel
IEEE Design & Test of Computers 13 (3), 79-86, 1996
Experiences with a synchronous virtual classroom in distance education
H Koppelman, H Vranken
ACM SIGCSE Bulletin 40 (3), 194-198, 2008
A survey of authentication and communications security in online banking
S Kiljan, K Simoens, DD Cock, MV Eekelen, H Vranken
ACM Computing Surveys (CSUR) 49 (4), 1-35, 2016
Evaluation of transaction authentication methods for online banking
S Kiljan, H Vranken, M van Eekelen
Future Generation Computer Systems 80, 430-447, 2018
Redundancy modelling and array yield analysis for repairable embedded memories
A Sehgal, A Dubey, EJ Marinissen, C Wouters, H Vranken, K Chakrabarty
IEE Proceedings-Computers and Digital Techniques 152 (1), 97-106, 2005
Fault detection and diagnosis with parity trees for space compaction of test responses
H Vranken, SK Goel, A Glowatz, J Schloeffel, F Hapke
Proceedings of the 43rd annual Design Automation Conference, 1095-1098, 2006
Impact of test point insertion on silicon area and timing during layout
H Vranken, FS Sapei, HJ Wunderlich
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
On the role of DfT in IC-ATE matching
EJ Marinissen, H Vranken
Digest of Papers of IEEE International Workshop on Test Resource …, 2001
Circuit partitioning for efficient logic BIST synthesis
A Irion, G Kiefer, H Vranken, HJ Wunderlich
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
Testing of an integrated circuit that contains secret information
EJ Marinissen, SK Goel, AK Nieuwland, HGH Vermuelen, HPE Vranken
US Patent 9,041,411, 2015
A distributed virtual computer security lab with central authority.
J Haag, T Horsmann, S Karsch, HPE Vranken
CSERC 11, 89-95, 2011
Discovering software vulnerabilities using data-flow analysis and machine learning
J Kronjee, A Hommersom, H Vranken
Proceedings of the 13th International Conference on Availability …, 2018
The role of Internet Service Providers in botnet mitigation
J Pijpker, H Vranken
2016 European Intelligence and Security Informatics Conference (EISIC), 24-31, 2016
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