Steven Derrien
Steven Derrien
Université de Rennes 1
Verified email at irisa.fr
TitleCited byYear
High-level synthesis: from algorithm to digital circuit
P Coussy, A Morawiec
Springer, 2008
443*2008
Approximating a single viewpoint in panoramic imaging devices
S Derrien, K Konolige
Proceedings 2000 ICRA. Millennium Conference. IEEE International Conference …, 2000
772000
On model subtyping
C Guy, B Combemale, S Derrien, JRH Steel, JM Jézéquel
European Conference on Modelling Foundations and Applications, 400-415, 2012
742012
ompVerify: polyhedral analysis for the OpenMP programmer
V Basupalli, T Yuki, S Rajopadhye, A Morvan, S Derrien, P Quinton, ...
International Workshop on OpenMP, 37-53, 2011
462011
Polyhedral bubble insertion: A method to improve nested loop pipelining for high-level synthesis
A Morvan, S Derrien, P Quinton
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
392013
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking
MA Pasha, S Derrien, O Sentieys
Design Automation Conference, 693-698, 2010
392010
Parallelizing HMMER for hardware acceleration on FPGAs
S Derrien, P Quinton
2007 IEEE International Conf. on Application-specific Systems, Architectures …, 2007
352007
Runtime dependency analysis for loop pipelining in high-level synthesis
M Alle, A Morvan, S Derrien
Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013
322013
Combined instruction and loop parallelism in array synthesis for FPGAs
S Derrien, S Rajopadhye, SS Kolay
Proceedings of the 14th international symposium on Systems synthesis, 165-170, 2001
32*2001
A Reconfigurable Parallel Disk System for Filtering Genomic Banks.
D Lavenier, S Guyetant, S Derrien, S Rubini
Engineering of Reconfigurable Systems and Algorithms 2, 154-166, 2003
302003
GeCoS: A framework for prototyping custom hardware design flows
A Floc'h, T Yuki, A El-Moussawi, A Morvan, K Martin, M Naullet, M Alle, ...
2013 IEEE 13th International Working Conference on Source Code Analysis and …, 2013
252013
Tightening contention delays while scheduling parallel applications on multi-core architectures
B Rouxel, S Derrien, I Puaut
ACM Transactions on Embedded Computing Systems (TECS) 16 (5s), 1-20, 2017
232017
Cluster of re-configurable nodes for scanning large genomic banks
S Guyetant, M Giraud, L L’Hours, S Derrien, S Rubini, D Lavenier, ...
Parallel Computing 31 (1), 73-96, 2005
232005
Loop tiling for reconfigurable accelerators
S Derrien, S Rajopadhye
International Conference on Field Programmable Logic and Applications, 398-408, 2001
232001
Toward ultra low-power hardware specialization of a wireless sensor network node
MA Pasha, S Derrien, O Sentieys
2009 IEEE 13th International Multitopic Conference, 1-6, 2009
222009
Method and apparatus for panoramic imaging
K Konolige, S Derrien
US Patent 6,545,702, 2003
212003
High-level synthesis of loops using the polyhedral model
S Derrien, S Rajopadhye, P Quinton, T Risset
High-level synthesis, 215-230, 2008
192008
Acceleration of a content-based image-retrieval application on the RDISK cluster
A Noumsi, S Derrien, P Quinton
Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006
192006
System-level synthesis for wireless sensor node controllers: A complete design flow
MA Pasha, S Derrien, O Sentieys
ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (1 …, 2012
172012
Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion
A Morvan, S Derrien, P Quinton
2011 International Conference on Field-Programmable Technology, 1-10, 2011
172011
The system can't perform the operation now. Try again later.
Articles 1–20