Ilia Polian - Citazioni di Google Scholar

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Indice H	29	17
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Bernd BeckerProfessor of Computer Science, University of FreiburgEmail verificata su informatik.uni-freiburg.de
Matthias SauerUniversität FreiburgEmail verificata su informatik.uni-freiburg.de
John P HayesProfessor of EECS, University of MichiganEmail verificata su umich.edu
Hans-Joachim WunderlichProfessor of Computer Science, University of StuttgartEmail verificata su informatik.uni-stuttgart.de
Sudhakar ReddyDepartment of ECE, University of IowaEmail verificata su engineering.uiowa.edu
Alexandru PalerJohannes Kepler University, Linz, AustriaEmail verificata su jku.at
Sandip KunduUniversity of MassachusettsEmail verificata su ecs.umass.edu
Simon DevittUniversity of Technology, SydneyEmail verificata su uts.edu.au
Sybille HellebrandUniversity of Paderborn, GermanyEmail verificata su uni-paderborn.de
Philipp JovanovicÉcole Polytechnique Fédérale de LausanneEmail verificata su jovanovic.io
Mariane ComteLIRMM, Université de MontpellierEmail verificata su umontpellier.fr
Martin KreuzerUniversity of PassauEmail verificata su uni-passau.de
Raghavan KumarIntel LabsEmail verificata su intel.com
Osnat KerenFaculty of Engineering , Bar-Ilan UniversityEmail verificata su biu.ac.il
Jan ReinekeProfessor of Computer Science, Saarland University, Saarland Informatics CampusEmail verificata su cs.uni-saarland.de
Reinhard WilhelmComputer Science, Saarland University, Saarland Informatics Campus (SIC)Email verificata su cs.uni-saarland.de
Björn WachterUniversity of OxfordEmail verificata su cs.ox.ac.uk
Irith PomeranzPurdue UniversityEmail verificata su ecn.purdue.edu
Oliver PaulProfessor for Microsystems Engineering, University of FreiburgEmail verificata su imtek.de
Patrick RutherSenior Scientist, Department of Microsystems Engineering (IMTEK), University of Freiburg, GermanyEmail verificata su imtek.de

Ilia Polian

University of Stuttgart

Email verificata su polian.de - Home page

Hardware security Emerging architectures Test and reliability


Titolo	Citata da	Anno
A definition and classification of timing anomalies J Reineke, B Wachter, S Thesing, R Wilhelm, I Polian, J Eisinger, ... 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06), 2006	216	2006
A family of logical fault models for reversible circuits I Polian, T Fiehn, B Becker, JP Hayes 14th Asian Test Symposium (ATS'05), 422-427, 2005	119	2005
X-masking during logic BIST and its impact on defect coverage Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ... 2004 International Conferce on Test, 442-451, 2004	109	2004
Testing for missing-gate faults in reversible circuits JP Hayes, I Polian, B Becker 13th Asian test symposium, 100-105, 2004	101	2004
Simulating resistive-bridging and stuck-at faults P Engelke, I Polian, M Renovell, B Becker IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006	89	2006
An analysis framework for transient-error tolerance JP Hayes, I Polian, B Becker 25th IEEE VLSI Test Symposium (VTS'07), 249-255, 2007	74	2007
Adaptive voltage over-scaling for resilient applications PK Krause, I Polian 2011 Design, Automation & Test in Europe, 1-6, 2011	64	2011
A fault attack on the LED block cipher P Jovanovic, M Kreuzer, I Polian International Workshop on Constructive Side-Channel Analysis and Secure …, 2012	63	2012
Power droop testing I Polian, A Czutro, S Kundu, B Becker 2006 International Conference on Computer Design, 243-250, 2006	63	2006
Analysis and optimization of fault-tolerant embedded systems with hardened processors V Izosimov, I Polian, P Pop, P Eles, Z Peng 2009 Design, Automation & Test in Europe Conference & Exhibition, 682-687, 2009	58	2009
Functional constraints vs. test compression in scan-based delay testing I Polian, H Fujiwara Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006	55	2006
A simulator of small-delay faults caused by resistive-open defects A Czutro, N Houarche, P Engelke, I Polian, M Comte, M Renovell, ... 2008 13th European Test Symposium, 113-118, 2008	52	2008
Small-delay-fault ATPG with waveform accuracy M Sauer, A Czutro, I Polian, B Becker 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 30-36, 2012	51	2012
Resistive bridge fault model evolution from conventional to ultra deep submicron I Polian, P Engelke, B Becker, S Kundu, JM Galliere, M Renovell 23rd IEEE VLSI Test Symposium (VTS'05), 343-348, 2005	51	2005
Parametric trojans for fault-injection attacks on cryptographic hardware R Kumar, P Jovanovic, W Burleson, I Polian 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 18-28, 2014	50	2014
Automatic test pattern generation for interconnect open defects S Spinner, I Polian, P Engelke, B Becker, M Keim, WT Cheng 26th IEEE VLSI Test Symposium (vts 2008), 181-186, 2008	50	2008
Selective hardening: Toward cost-effective error tolerance I Polian, JP Hayes IEEE Design & Test of Computers 28 (3), 54-63, 2010	44	2010
Modeling and mitigating transient errors in logic circuits I Polian, JP Hayes, SM Reddy, B Becker IEEE Transactions on Dependable and Secure Computing 8 (4), 537-547, 2011	43	2011
Automatic test pattern generation for resistive bridging faults P Engelke, I Polian, M Renovell, B Becker Proceedings. 2004 IEEE International Workshop on Current and Defect Based …, 2004	43	2004
The pros and cons of very-low-voltage testing: an analysis based on resistive bridging faults P Engelke, I Polian, M Renovell, B Seshadri, B Becker 22nd IEEE VLSI Test Symposium, 2004. Proceedings., 171-178, 2004	41	2004

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