Ilia Polian

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	Tutte	Dal 2016
Citazioni	3291	1277
Indice H	30	17
i10-index	87	40

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Bernd BeckerProfessor of Computer Science, University of FreiburgEmail verificata su informatik.uni-freiburg.de
John P HayesProfessor of EECS, University of MichiganEmail verificata su umich.edu
Matthias SauerUniversität FreiburgEmail verificata su informatik.uni-freiburg.de
Hans-Joachim WunderlichProfessor of Computer Science, University of StuttgartEmail verificata su informatik.uni-stuttgart.de
Sudhakar ReddyDepartment of ECE, University of IowaEmail verificata su engineering.uiowa.edu
Alexandru PalerJohannes Kepler University, Linz, AustriaEmail verificata su jku.at
Sandip KunduUniversity of MassachusettsEmail verificata su ecs.umass.edu
Mariane ComteLIRMM, Université de MontpellierEmail verificata su umontpellier.fr
Martin KreuzerUniversity of PassauEmail verificata su uni-passau.de
Simon DevittUniversity of Technology SydneyEmail verificata su uts.edu.au
Sybille HellebrandUniversity of Paderborn, GermanyEmail verificata su uni-paderborn.de
Philipp JovanovicUniversity College LondonEmail verificata su jovanovic.io
Osnat KerenFaculty of Engineering , Bar-Ilan UniversityEmail verificata su biu.ac.il
Reinhard WilhelmComputer Science, Saarland University, Saarland Informatics Campus (SIC)Email verificata su cs.uni-saarland.de
Hideo Fujiwara 藤原秀雄Professor, Osaka Gakuin University: Professor Emeritus, NAISTEmail verificata su fujiwaralab.net
Raghavan KumarIntel LabsEmail verificata su intel.com
Jan ReinekeProfessor of Computer Science, Saarland University, Saarland Informatics CampusEmail verificata su cs.uni-saarland.de
Irith PomeranzPurdue UniversityEmail verificata su ecn.purdue.edu
Zebo PengProfessor of Computer Systems, Linkoping UniversityEmail verificata su liu.se
Viacheslav IzosimovResearcher, The Royal Institute of Technology (KTH)Email verificata su kth.se

Ilia Polian

University of Stuttgart

Email verificata su polian.de - Home page

Hardware security Emerging architectures Test and reliability


Titolo Ordina per citazioni Ordina per anno Ordina per titolo	Citata da Citata da	Anno
A definition and classification of timing anomalies J Reineke, B Wachter, S Thesing, R Wilhelm, I Polian, J Eisinger, ... 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06), 2006	243	2006
A family of logical fault models for reversible circuits I Polian, T Fiehn, B Becker, JP Hayes 14th Asian Test Symposium (ATS'05), 422-427, 2005	133	2005
X-masking during logic BIST and its impact on defect coverage Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ... 2004 International Conferce on Test, 442-451, 2004	121	2004
Testing for missing-gate faults in reversible circuits JP Hayes, I Polian, B Becker 13th Asian test symposium, 100-105, 2004	120	2004
Simulating resistive-bridging and stuck-at faults P Engelke, I Polian, M Renovell, B Becker IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006	99	2006
An analysis framework for transient-error tolerance JP Hayes, I Polian, B Becker 25th IEEE VLSI Test Symposium (VTS'07), 249-255, 2007	77	2007
Adaptive voltage over-scaling for resilient applications PK Krause, I Polian 2011 Design, Automation & Test in Europe, 1-6, 2011	72	2011
A fault attack on the LED block cipher P Jovanovic, M Kreuzer, I Polian International Workshop on Constructive Side-Channel Analysis and Secure …, 2012	71	2012
Power droop testing I Polian, A Czutro, S Kundu, B Becker 2006 International Conference on Computer Design, 243-250, 2006	68	2006
Analysis and optimization of fault-tolerant embedded systems with hardened processors V Izosimov, I Polian, P Pop, P Eles, Z Peng 2009 Design, Automation & Test in Europe Conference & Exhibition, 682-687, 2009	67	2009
Parametric trojans for fault-injection attacks on cryptographic hardware R Kumar, P Jovanovic, W Burleson, I Polian 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 18-28, 2014	64	2014
A simulator of small-delay faults caused by resistive-open defects A Czutro, N Houarche, P Engelke, I Polian, M Comte, M Renovell, ... 2008 13th European Test Symposium, 113-118, 2008	63	2008
Small-delay-fault ATPG with waveform accuracy M Sauer, A Czutro, I Polian, B Becker 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 30-36, 2012	57	2012
Functional constraints vs. test compression in scan-based delay testing I Polian, H Fujiwara Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006	56	2006
Automatic test pattern generation for interconnect open defects S Spinner, I Polian, P Engelke, B Becker, M Keim, WT Cheng 26th IEEE VLSI Test Symposium (vts 2008), 181-186, 2008	55	2008
Resistive bridge fault model evolution from conventional to ultra deep submicron I Polian, P Engelke, B Becker, S Kundu, JM Galliere, M Renovell 23rd IEEE VLSI Test Symposium (VTS'05), 343-348, 2005	54	2005
Selective hardening: Toward cost-effective error tolerance I Polian, JP Hayes IEEE Design & Test of Computers 28 (3), 54-63, 2010	50	2010
Modeling and mitigating transient errors in logic circuits I Polian, JP Hayes, SM Reddy, B Becker IEEE Transactions on Dependable and Secure Computing 8 (4), 537-547, 2011	47	2011
A study of cognitive resilience in a JPEG compressor D Nowroth, I Polian, B Becker 2008 IEEE International Conference on Dependable Systems and Networks With …, 2008	45	2008
Selective hardening in early design steps CG Zoellin, HJ Wunderlich, I Polian, B Becker 2008 13th European test symposium, 185-190, 2008	44	2008

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