Joseph J. Nahas
Joseph J. Nahas
Visiting Professor, Department of Computer Science and Engineering, University of Notre Dame
Email verificata su nd.edu
Titolo
Citata da
Citata da
Anno
Why'nearshore'means that distance matters
E Carmel, P Abbott
Communications of the ACM 50 (10), 40-46, 2007
2082007
Nanomagnet logic: progress toward system-level integration
MT Niemier, GH Bernstein, G Csaba, A Dingler, XS Hu, S Kurtz, S Liu, ...
Journal of Physics: Condensed Matter 23 (49), 493202, 2011
1952011
A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers
TW Andre, JJ Nahas, CK Subramanian, BJ Garni, HS Lin, A Omair, ...
IEEE journal of solid-state circuits 40 (1), 301-309, 2005
1772005
Sense amplifier bias circuit for a memory having at least two distinct resistance states
JJ Nahas, TW Andre, BJ Garni
US Patent 6,700,814, 2004
1702004
A 0.18/spl mu/m 4Mb toggling MRAM
M Durlam, D Addie, J Akerman, B Butcher, P Brown, J Chan, M DeHerrera, ...
IEEE International Electron Devices Meeting 2003, 34.6. 1-34.6. 3, 2003
1312003
Two-dimensional heterojunction interlayer tunneling field effect transistors (Thin-TFETs)
MO Li, D Esseni, JJ Nahas, D Jena, HG Xing
IEEE Journal of the Electron Devices Society 3 (3), 200-207, 2015
1142015
Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics
CK Subramanian, JJ Nahas
US Patent 6,944,052, 2005
952005
Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics
CK Subramanian, JJ Nahas
US Patent 6,944,052, 2005
932005
Analog circuit design using tunnel-FETs
B Sedighi, XS Hu, H Liu, JJ Nahas, M Niemier
IEEE transactions on circuits and systems I: regular papers 62 (1), 39-48, 2014
832014
Demonstrated reliability of 4-Mb MRAM
J Akerman, P Brown, M DeHerrera, M Durlam, E Fuchs, D Gajewski, ...
IEEE Transactions on Device and Materials Reliability 4 (3), 428-435, 2004
742004
Migrating tasks between asymmetric computing elements of a multi-core processor
A Naveh, Y Yosef, E Weissmann, A Aggarwal, E Rotem, A Mendelson, ...
US Patent 10,185,566, 2019
60*2019
Migrating tasks between asymmetric computing elements of a multi-core processor
A Naveh, Y Yosef, E Weissmann, A Aggarwal, E Rotem, A Mendelson, ...
US Patent 10,185,566, 2019
60*2019
MRAM and methods for reading the MRAM
MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ...
US Patent 6,909,631, 2005
542005
MRAM and methods for reading the MRAM
MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ...
US Patent 6,909,631, 2005
542005
MRAM and methods for reading the MRAM
MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ...
US Patent 6,909,631, 2005
542005
MRAM and methods for reading the MRAM
MA Durlam, TW Andre, MF Deherrera, BN Engel, BJ Garni, JJ Nahas, ...
US Patent 6,909,631, 2005
542005
Modeling and computer simulation of a microwave-to-dc energy conversion element
JJ Nahas
IEEE Transactions on Microwave Theory and Techniques 23 (12), 1030-1035, 1975
511975
Sense amplifier for a memory having at least two distinct resistance states
JJ Nahas, TW Andre, BJ Garni, CK Subramanian
US Patent 6,600,690, 2003
502003
Sense amplifier for a memory having at least two distinct resistance states
JJ Nahas, TW Andre, BJ Garni, CK Subramanian
US Patent 6,600,690, 2003
502003
Sense amplifier for a memory having at least two distinct resistance states
JJ Nahas, TW Andre, BJ Garni, CK Subramanian
US Patent 6,600,690, 2003
502003
Il sistema al momento non pu eseguire l'operazione. Riprova pi tardi.
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