Marie-Lise Flottes
Marie-Lise Flottes
Email verificata su lirmm.fr
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Citata da
Citata da
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A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans
S Dupuis, PS Ba, G Di Natale, ML Flottes, B Rouzeyre
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 49-54, 2014
2022014
Scan design and secure chip [secure IC testing]
D Hély, ML Flottes, F Bancel, B Rouzeyre, N Berard, M Renovell
IOLTS: International On-Line Testing Symposium, 219-224, 2004
1882004
Test control for secure scan designs
D Hely, F Bancel, ML Flottes, B Rouzeyre
European Test Symposium (ETS'05), 190-195, 2005
1012005
Test versus security: Past and present
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
IEEE Transactions on Emerging topics in Computing 2 (1), 50-62, 2014
862014
Are advanced DfT structures sufficient for preventing scan-attacks?
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2012 IEEE 30th VLSI Test Symposium (VTS), 246-251, 2012
712012
New security threats against chips containing scan chain structures
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
2011 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2011
712011
Scan attacks and countermeasures in presence of scan response compactors
J DaRolt, G Di Natale, ML Flottes, B Rouzeyre
2011 Sixteenth IEEE European Test Symposium, 19-24, 2011
582011
A novel differential scan attack on advanced DFT structures
JD Rolt, GD Natale, ML Flottes, B Rouzeyre
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013
562013
Secure scan techniques: a comparison
D Hely, F Bancel, ML Flottes, B Rouzeyre
12th IEEE International On-Line Testing Symposium (IOLTS'06), 6 pp., 2006
552006
A reliable architecture for parallel implementations of the advanced encryption standard
G Di Natale, M Doulcier, ML Flottes, B Rouzeyre
Journal of Electronic Testing 25 (4), 269-278, 2009
542009
Securing scan control in crypto chips
D Hély, F Bancel, ML Flottes, B Rouzeyre
Journal of Electronic Testing 23 (5), 457-464, 2007
502007
Self-test techniques for crypto-devices
G Di Natale, M Doulcier, ML Flottes, B Rouzeyre
IEEE transactions on very large scale integration (VLSI) systems 18 (2), 329-333, 2009
452009
Analyzing testability from behavioral to RT level
ML Flottes, R Pires, B Rouzeyre
Proceedings European Design and Test Conference. ED & TC 97, 158-165, 1997
431997
Secure JTAG implementation using Schnorr protocol
A Das, J Da Rolt, S Ghosh, S Seys, S Dupuis, G Di Natale, ML Flottes, ...
Journal of Electronic Testing 29 (2), 193-209, 2013
422013
AES-based BIST: self-test, test pattern generation and signature analysis
M Doulcier, ML Flottes, B Rouzeyre
4th IEEE International Symposium on Electronic Design, Test and Applications …, 2008
372008
A new scan attack on rsa in presence of industrial countermeasures
J Da Rolt, A Das, G Di Natale, ML Flottes, B Rouzeyre, I Verbauwhede
International Workshop on Constructive Side-Channel Analysis and Secure …, 2012
362012
High-level synthesis for easy testability
ML Flottes, D Hammad, B Rouzeyre
Proceedings the European Design and Test Conference. ED&TC 1995, 198-206, 1995
361995
Protection against hardware trojans with logic testing: Proposed solutions and challenges ahead
S Dupuis, ML Flottes, G Di Natale, B Rouzeyre
IEEE Design & Test 35 (2), 73-90, 2017
342017
Thwarting scan-based attacks on secure-ICs with on-chip comparison
J Da Rolt, G Di Natale, ML Flottes, B Rouzeyre
IEEE transactions on very large scale integration (VLSI) systems 22 (4), 947-951, 2013
342013
An efficient approach to SoC wrapper design, TAM configuration and test scheduling
J Pouget, E Larsson, Z Peng, ML Flottes, B Rouzeyre
The Eighth IEEE European Test Workshop, 2003. Proceedings., 51-56, 2003
322003
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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