Lawrence Pileggi
Lawrence Pileggi
Professor of ECE, Carnegie Mellon University
Verified email at andrew.cmu.edu
TitleCited byYear
Asymptotic waveform evaluation for timing analysis
LT Pillage, RA Rohrer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990
20291990
PRIMA: Passive reduced-order interconnect macromodeling algorithm
A Odabasioglu, M Celik, LT Pileggi, LT Pileggi, LT Pileggi
Proceedings of the 1997 IEEE/ACM international conference on Computer-aided …, 1997
18011997
Electronic Circuit & System Simulation Methods (SRE)
L Pillage
McGraw-Hill, Inc., 1998
5071998
Electronic Circuit & System Simulation Methods (SRE)
L Pillage
McGraw-Hill, Inc., 1998
5071998
Modeling the" Effective capacitance" for the RC interconnect of CMOS gates
J Qian, S Pullela, L Pillage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
3861994
IC interconnect analysis
M Celik, L Pileggi, L Pileggi, A Odabasioglu
Springer Science & Business Media, 2002
3242002
The Elmore delay as a bound for RC trees with generalized input signals
R Gupta
32nd Design Automation Conference, 364-369, 1995
2861995
Programmable gate array based on configurable metal interconnect vias
L Pileggi, H Schmit
US Patent 6,633,182, 2003
2572003
Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
LT Pileggi, AJ Strojwas, LL Lanza
US Patent 7,278,118, 2007
227*2007
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Y Zhan, AJ Strojwas, X Li, LT Pileggi, D Newmark, M Sharma
Proceedings of the 42nd annual Design Automation Conference, 77-82, 2005
2092005
RICE: Rapid interconnect circuit evaluator
CL Ratzlaff, N Gopal, LT Pillage
Proceedings of the 28th ACM/IEEE Design Automation Conference, 555-560, 1991
2091991
Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
LT Pileggi, AJ Strojwas, LL Lanza
US Patent 7,906,254, 2011
2082011
Digital circuit design challenges and opportunities in the era of nanoscale CMOS
BH Calhoun, Y Cao, X Li, K Mai, LT Pileggi, RA Rutenbar, KL Shepard
Proceedings of the IEEE 96 (2), 343-365, 2008
2032008
RICE: Rapid interconnect circuit evaluation using AWE
CL Ratzlaff, LT Pillage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
1981994
RICE: Rapid interconnect circuit evaluation using AWE
CL Ratzlaff, LT Pillage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
1981994
RICE: Rapid interconnect circuit evaluation using AWE
CL Ratzlaff, LT Pillage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
1981994
Calculating worst-case gate delays due to dominant capacitance coupling
F Dartu, LT Pileggi, LT Pileggi, LT Pileggi
Proceedings of the 34th annual Design Automation Conference, 46-51, 1997
1841997
Model order-reduction of RC (L) interconnect including variational analysis
Y Liu, LT Pileggi, AJ Strojwas
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 201-206, 1999
1801999
Performance computation for precharacterized CMOS gates with RC loads
F Dartu, N Menezes, LT Pileggi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996
1721996
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Y Liu, SR Nassif, LT Pileggi, LT Pileggi, LT Pileggi, AJ Strojwas
Proceedings of the 37th Annual Design Automation Conference, 168-171, 2000
1682000
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