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Dr. Balwinder Raj
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Recent advances and progress in development of the field effect transistor biosensor: A review
T Wadhera, D Kakkar, G Wadhwa, B Raj
Journal of Electronic Materials 48, 7635-7646, 2019
1472019
A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis
G Singh, RK Sarin, B Raj
Journal of Computational Electronics 15, 455-465, 2016
1292016
Label free detection of biomolecules using charge-plasma-based gate underlap dielectric modulated junctionless TFET
G Wadhwa, B Raj
Journal of Electronic Materials 47, 4683-4693, 2018
1242018
Nanoscale FinFET based SRAM cell design: Analysis of performance metric, process variation, underlapped FinFET, and temperature effect
B Raj, AK Saxena, S Dasgupta
IEEE Circuits and Systems Magazine 11 (3), 38-50, 2011
1232011
Design, simulation and performance analysis of JLTFET biosensor for high sensitivity
G Wadhwa, B Raj
IEEE Transactions on nanotechnology 18, 567-574, 2019
1122019
Design and investigation of 7T2M-NVSRAM with enhanced stability and temperature impact on store/restore energy
J Singh, B Raj
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (6 …, 2019
812019
INDEP approach for leakage reduction in nanoscale CMOS circuits
VK Sharma, M Pattanaik, B Raj
International Journal of Electronics 102 (2), 200-215, 2015
792015
ONOFIC approach: low power high speed nanoscale VLSI circuits design
VK Sharma, M Pattanaik, B Raj
International Journal of Electronics 101 (1), 61-73, 2014
792014
Design and analysis of a heterojunction vertical t-shaped tunnel field effect transistor
S Singh, B Raj
Journal of Electronic Materials 48, 6253-6260, 2019
772019
Parametric variation analysis of symmetric double gate charge plasma JLTFET for biosensor application
G Wadhwa, B Raj
IEEE Sensors Journal 18 (15), 6070-6077, 2018
732018
Analytical modeling of split-gate junction-less transistor for a biosensor application
S Singh, B Raj, SK Vishvakarma
Sensing and bio-sensing research 18, 31-36, 2018
662018
Modeling and simulation analysis of SiGe heterojunction double gate vertical t-shaped tunnel FET
S Singh, B Raj
Superlattices and Microstructures 142, 106496, 2020
602020
An accurate and generic window function for nonlinear memristor models
J Singh, B Raj
Journal of Computational Electronics 18, 640-647, 2019
592019
A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications
C Goyal, JS Ubhi, B Raj
International Journal of Circuit Theory and Applications 47 (9), 1446-1458, 2019
582019
Fault‐tolerant design and analysis of QCA‐based circuits
G Singh, B Raj, RK Sarin
IET Circuits, Devices & Systems 12 (5), 638-644, 2018
582018
Modeling of mean barrier height levying various image forces of metal–insulator–metal structure to enhance the performance of conductive filament based memristor model
J Singh, B Raj
IEEE Transactions on Nanotechnology 17 (2), 268-275, 2018
582018
Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM
A Singh, M Khosla, B Raj
AEU-International Journal of Electronics and Communications 80, 67-72, 2017
572017
PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits
VK Sharma, M Pattanaik, B Raj
Microelectronics reliability 54 (1), 90-99, 2014
572014
Temperature dependent analytical modeling and simulations of nanoscale memristor
J Singh, B Raj
Engineering science and technology, an international journal 21 (5), 862-868, 2018
552018
Compact channel potential analytical modeling of DG-TFET based on Evanescent-mode approach
S Kumar, B Raj
Journal of Computational Electronics 14, 820-827, 2015
552015
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