| Design issues and considerations for low-cost 3-D TSV IC technology G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ... IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2011 | 393 | 2011 |
| Designing Application-Specific Networks on Chips with Floorplan Information S Murali, P Meloni, F Angiolini, D Atienza, S Carta, L Benini, G De Micheli, ... Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided …, 2006 | 261 | 2006 |
| Analyzing on-chip communication in a MPSoC environment M Loghi, F Angiolini, D Bertozzi, L Benini, R Zafalon Design, Automation and Test in Europe Conference and Exhibition, 2004 …, 2004 | 248 | 2004 |
| Network-on-Chip design and synthesis outlook D Atienza, F Angiolini, S Murali, A Pullini, L Benini, G De Micheli INTEGRATION, the VLSI journal 41 (3), 340-359, 2008 | 208 | 2008 |
| An integrated open framework for heterogeneous MPSoC design space exploration F Angiolini, J Ceng, R Leupers, F Ferrari, C Ferri, L Benini Proceedings of the conference on Design, automation and test in Europe …, 2006 | 202* | 2006 |
| × pipes lite: A synthesis oriented design library for networks on chips S Stergiou, F Angiolini, S Carta, L Raffo, D Bertozzi, G De Micheli Design, Automation and Test in Europe, 2005. Proceedings, 1188-1193, 2005 | 192 | 2005 |
| Fault tolerance overhead in network-on-chip flow control schemes A Pullini, F Angiolini, D Bertozzi, L Benini Proceedings of the 18th annual symposium on Integrated circuits and system …, 2005 | 139 | 2005 |
| A post-compiler approach to scratchpad mapping of code F Angiolini, F Menichelli, A Ferrero, L Benini, M Olivieri Proceedings of the 2004 international conference on Compilers, architecture …, 2004 | 138 | 2004 |
| Contrasting a NoC and a traditional interconnect fabric with layout awareness F Angiolini, P Meloni, S Carta, L Benini, L Raffo Proceedings of the conference on Design, automation and test in Europe …, 2006 | 128 | 2006 |
| Polynomial-time algorithm for on-chip scratchpad memory partitioning F Angiolini, L Benini, A Caprara Proceedings of the 2003 international conference on Compilers, architecture …, 2003 | 128 | 2003 |
| Bringing NoCs to 65 nm A Pullini, F Angiolini, S Murali, D Atienza, G De Micheli, L Benini IEEE Micro 27 (5), 75-85, 2007 | 101 | 2007 |
| A network traffic generator model for fast network-on-chip simulation S Mahadevan, F Angiolini, J Sparsø, M Storgaard, J Madsen, RG Olsen Design, Automation, and Test in Europe, 173-184, 2008 | 94 | 2008 |
| Networks on Chips: from Research to Products G De Micheli, C Seiculescu, S Murali, L Benini, F Angiolini, A Pullini 47th ACM/IEEE Design Automation Conference (DAC), 300-305, 2010 | 93 | 2010 |
| Networks on Chips: From Research to Products A Pullini, F Angiolini, G De Micheli, C Seiculescu, L Benini, S Murali 47th ACM/IEEE Design Automation Conference (DAC), 2010 | 93* | 2010 |
| Networks on chips: from research to products G De Micheli, C Seiculescu, S Murali, L Benini, F Angiolini, A Pullini Design Automation Conference (DAC), 2010 47th ACM/IEEE, 300-305, 2010 | 93 | 2010 |
| Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip I Loi, F Angiolini, S Fujita, S Mitra, L Benini IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 89 | 2011 |
| Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow I Loi, F Angiolini, L Benini Proceedings of the 2nd international conference on Nano-Networks, 15, 2007 | 86 | 2007 |
| A layout-aware analysis of networks-on-chip and traditional interconnects for MPSoCs F Angiolini, P Meloni, SM Carta, L Raffo, L Benini IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 84 | 2007 |
| An efficient profile-based algorithm for scratchpad memory partitioning F Angiolini, L Benini, A Caprara IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 81 | 2005 |
| NoC design and implementation in 65nm technology A Pullini, F Angiolini, P Meloni, D Atienza, S Murali, L Raffo, G De Micheli, ... Proceedings of the First International Symposium on Networks-on-Chip, 273-282, 2007 | 80 | 2007 |
Luca BeniniETH Zürich, Università di BolognaEmail verificata su unibo.it
