| A CORDIC based configurable activation function for ANN applications G Raut, S Rai, SK Vishvakarma, A Kumar 2020 IEEE computer society annual symposium on VLSI (ISVLSI), 78-83, 2020 | 26 | 2020 |
| An accurate and noninvasive skin cancer screening based on imaging technique G Rajput, S Agrawal, G Raut, SK Vishvakarma International Journal of Imaging Systems and Technology 32 (1), 354-368, 2022 | 24 | 2022 |
| RECON: resource-efficient CORDIC-based neuron architecture G Raut, S Rai, SK Vishvakarma, A Kumar IEEE Open Journal of Circuits and Systems 2, 170-181, 2021 | 23 | 2021 |
| VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators G Rajput, G Raut, M Chandra, SK Vishvakarma Microprocessors and Microsystems 84, 104270, 2021 | 18 | 2021 |
| Data multiplexed and hardware reused architecture for deep neural network accelerator G Raut, A Biasizzo, N Dhakad, N Gupta, G Papa, SK Vishvakarma Neurocomputing 486, 147-159, 2022 | 12 | 2022 |
| Efficient low-precision cordic algorithm for hardware implementation of artificial neural network G Raut, V Bhartiy, G Rajput, S Khan, A Beohar, SK Vishvakarma VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 9 | 2019 |
| A 2.4-GS/s power-efficient, high-resolution reconfigurable dynamic comparator for ADC architecture G Raut, AP Shah, V Sharma, G Rajput, SK Vishvakarma Circuits, Systems, and Signal Processing 39 (9), 4681-4694, 2020 | 8 | 2020 |
| Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits N Gupta, AP Shah, RS Kumar, G Raut, NS Dhakad, SK Vishvakarma Microelectronics Reliability 117, 114013, 2021 | 6 | 2021 |
| BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator H Chhajed, G Raut, N Dhakad, S Vishwakarma, SK Vishvakarma Circuits, Systems, and Signal Processing, 1-16, 2022 | 5 | 2022 |
| An empirical approach to enhance performance for scalable cordic-based deep neural networks G Raut, S Karkun, SK Vishvakarma ACM Transactions on Reconfigurable Technology and Systems 16 (3), 1-32, 2023 | 2 | 2023 |
| An empirical evaluation of enhanced performance softmax function in deep learning S Mehra, G Raut, RD Purkayastha, SK Vishvakarma, A Biasizzo IEEE Access 11, 34912-34924, 2023 | 2 | 2023 |
| An ultra low power AES architecture for IoT S Khan, N Gupta, G Raut, G Rajput, JG Pandey, SK Vishvakarma International Symposium on VLSI Design and Test, 334-344, 2019 | 2 | 2019 |
| Compact spiking neural network system with SiGe based cylindrical tunneling transistor for low power applications A Beohar, G Raut, G Rajput, A Vishwakarma, AP Shah, BS Renewal, ... VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 2 | 2019 |
| In-Memory Computing with 6T SRAM for Multi-operator Logic Design NS Dhakad, E Chittora, G Raut, V Sharma, SK Vishvakarma Circuits, Systems, and Signal Processing 43 (1), 646-660, 2024 | 1 | 2024 |
| Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs V Trivedi, K Lalwani, G Raut, A Khomane, N Ashar, SK Vishvakarma Circuits, Systems, and Signal Processing 42 (12), 7596-7614, 2023 | 1 | 2023 |
| Design and analysis of Posit Quire processing engine for neural network applications PJ Edavoor, A Raveendran, D Selvakumar, V Desalphine, G Raut 2023 36th International Conference on VLSI Design and 2023 22nd …, 2023 | 1 | 2023 |
| Design and Analysis of Cyl GAA-TFET-Based Cross-Coupled Voltage Doubler Circuit A Beohar, AP Shah, N Yadav, G Raut, SK Vishvakarma Microelectronics, Circuits and Systems: Select Proceedings of 7th …, 2021 | 1 | 2021 |
| QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit N Ashar, G Raut, V Trivedi, SK Vishvakarma, A Kumar IEEE Access 12, 43600-43614, 2024 | | 2024 |
| A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators S Vishwakarma, G Raut, NS Dhakad, SK Vishvakarma, D Ghai IFIP International Internet of Things Conference, 433-441, 2023 | | 2023 |
| Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators G Raut, J Mukala, V Sharma, SK Vishvakarma Circuits, Systems, and Signal Processing 42 (10), 6089-6115, 2023 | | 2023 |
Dr. Santosh Kumar VishvakarmaIndian Institute of Technology IndoreVerified email at iiti.ac.in
