| Inverse metal-assisted chemical etching produces smooth high aspect ratio InP nanostructures SH Kim, PK Mohseni, Y Song, T Ishihara, X Li Nano letters 15 (1), 641-648, 2015 | 98 | 2015 |
| III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications Y Song, C Zhang, R Dowdy, K Chabak, PK Mohseni, W Choi, X Li IEEE Electron Device Letters 35 (3), 324-326, 2014 | 84 | 2014 |
| Mobility enhancement technology for scaling of CMOS devices: overview and status Y Song, H Zhou, Q Xu, J Luo, H Yin, J Yan, H Zhong Journal of electronic materials 40, 1584-1612, 2011 | 81 | 2011 |
| Field effect transistor structure comprising a stack of vertically separated channel nanowires X Li, Y Song US Patent 9,224,809, 2015 | 68 | 2015 |
| Damage-free smooth-sidewall InGaAs nanopillar array by metal-assisted chemical etching L Kong, Y Song, JD Kim, L Yu, D Wasserman, WK Chim, SY Chiam, X Li ACS nano 11 (10), 10193-10205, 2017 | 45 | 2017 |
| Ultra-high aspect ratio InP junctionless FinFETs by a novel wet etching method Y Song, PK Mohseni, SH Kim, JC Shin, T Ishihara, I Adesida, X Li IEEE Electron Device Letters 37 (8), 970-973, 2016 | 40 | 2016 |
| High-performance silicon nanowire gate-all-around nMOSFETs fabricated on bulk substrate using CMOS-compatible process Y Song, H Zhou, Q Xu, J Niu, J Yan, C Zhao, H Zhong IEEE electron device letters 31 (12), 1377-1379, 2010 | 36 | 2010 |
| Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance K Cheng, Y Song, Z Bi US Patent US10832907B2, 2020 | 31 | 2020 |
| Method for manufacturing suspended fin and gate-all-around field effect transistor H Zhou, Y Song, Q Xu US Patent 8,361,869, 2013 | 29 | 2013 |
| Performance breakthrough in gate-all-around nanowire n-and p-type MOSFETs fabricated on bulk silicon substrate Y Song, Q Xu, J Luo, H Zhou, J Niu, Q Liang, C Zhao IEEE transactions on electron devices 59 (7), 1885-1890, 2012 | 24 | 2012 |
| Fabrication of Bulk-Si FinFET using CMOS compatible process H Zhou, Y Song, Q Xu, Y Li, H Yin Microelectronic engineering 94, 26-28, 2012 | 20 | 2012 |
| Scaling Junctionless Multigate Field-Effect Transistors by Step-doping XL Yi Song Applied Physics Letters 108, 223506, 2014 | 16 | 2014 |
| Source/drain technologies for the scaling of nanoscale CMOS device Y Song, H Zhou, Q Xu Solid State Sciences 13 (2), 294-305, 2011 | 14 | 2011 |
| Source/drain extension regions and air spacers for nanosheet field-effect transistor structures Y Song, Z Bi, K Cheng, C Liu US Patent US10892328B2, 2021 | 10 | 2021 |
| Vertically stacked individually tunable nanowire field effect transistors for low power operation with ultrahigh radio frequency linearity Y Song, J Luo, X Li Applied Physics Letters 101 (9), 2012 | 9 | 2012 |
| Fringe-induced barrier lowering (FIBL) included sub-threshold swing model for double-gate MOSFETs P Liang, J Jiang, Y Song Journal of Physics D: Applied Physics 41 (21), 215109, 2008 | 8 | 2008 |
| Area selective cyclic deposition for VFET top spacer Z Bi, K Cheng, Y Xu, Y Song US Patent US10749011B2, 2020 | 6 | 2020 |
| Airgap formation in BEOL interconnect structure using sidewall image transfer K Cheng, EA De Silva, J Li, Y Song, P Xu US Patent 10,490,447, 2019 | 6 | 2019 |
| Method for manufacturing a MOSFET with a surrounding gate of bulk Si Y Song, H Zhou, Q Xu US Patent 7,960,235, 2011 | 3 | 2011 |
| Design and optimization considerations for bulk gate-all-around nanowire MOSFETs Y Song, Q Xu, H Zhou, X Cai Semiconductor science and technology 24 (10), 105006, 2009 | 3 | 2009 |
