Hardware private circuits: From trivial composition to full verification G Cassiers, B Grégoire, I Levi, FX Standaert
IEEE Transactions on Computers 70 (10), 1677-1690, 2020
99 2020 DPA-secured quasi-adiabatic logic (SQAL) for low-power passive RFID tags employing S-boxes M Avital, H Dagan, I Levi, O Keren, A Fish
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (1), 149-156, 2014
77 2014 Spook: Sponge-based leakage-resistant authenticated encryption with a masked tweakable block cipher D Bellizia, F Berti, O Bronchain, G Cassiers, S Duval, C Guo, G Leander, ...
IACR Transactions on Symmetric Cryptology 2020 (S1), 295--349, 2020
71 2020 Dual mode logic—Design for energy efficiency and high performance I Levi, A Fish
IEEE access 1, 258-265, 2013
53 2013 Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI R Taco, I Levi, M Lanuzza, A Fish
Solid-State Electronics 117, 185-192, 2016
49 2016 Low voltage dual mode logic: Model analysis and parameter extraction I Levi, A Kaizerman, A Fish
Microelectronics journal 44 (6), 553-560, 2013
49 2013 High speed dual mode logic carry look ahead adder I Levi, O Bass, A Kaizerman, A Belenky, A Fish
2012 ieee international symposium on circuits and systems (ISCAS), 3037-3040, 2012
49 2012 Logical effort for CMOS-based dual mode logic gates I Levi, A Belenky, A Fish
IEEE Transactions on very large scale integration (VLSI) systems 22 (5 …, 2013
45 2013 Data-dependent delays as a barrier against power attacks I Levi, O Keren, A Fish
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (8), 2069-2078, 2015
38 2015 Reducing a masked Implementation’s effective security order with setup manipulations: And an explanation based on externally-amplified couplings I Levi, D Bellizia, FX Standaert
IACR Transactions on Cryptographic Hardware and Embedded Systems, 293-317, 2019
37 2019 An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI R Taco, I Levi, M Lanuzza, A Fish
IEEE Journal of Solid-State Circuits 54 (2), 560-568, 2018
35 2018 Low AND depth and efficient inverses: a guide on s-boxes for low-latency masking B Bilgin, L De Meyer, S Duval, I Levi, FX Standaert
IACR Transactions on Symmetric Cryptology 2020 (1), 144-184, 2020
33 2020 Towards secure composition of integrated circuits and electronic systems: On the role of EDA J Knechtel, EB Kavun, F Regazzoni, A Heuser, A Chattopadhyay, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 508-513, 2020
32 2020 Leakage power attack-resilient symmetrical 8T SRAM cell R Giterman, M Vicentowski, I Levi, Y Weizman, O Keren, A Fish
IEEE Transactions on very large scale integration (VLSI) systems 26 (10 …, 2018
31 2018 Ask less, get more: Side-channel signal hiding, revisited I Levi, D Bellizia, D Bol, FX Standaert
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4904-4917, 2020
25 2020 CPA secured data-dependent delay-assignment methodology I Levi, A Fish, O Keren
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 608-620, 2016
24 2016 Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design R Taco, I Levi, A Fish, M Lanuzza
2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel …, 2014
24 2014 Design flow and characterization methodology for dual mode logic V Yuzhaninov, I Levi, A Fish
IEEE Access 3, 3089-3101, 2015
22 2015 Low-cost pseudoasynchronous circuit design style with reduced exploitable side information I Levi, A Fish, O Keren
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 82-95, 2017
21 2017 CMOS based gates for blurring power information M Avital, I Levi, O Keren, A Fish
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (7), 1033-1042, 2016
16 2016