| On delay fault testing in logic circuits CJ Lin, SM Reddy Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1987 | 739 | 1987 |
| Easily Testable Realizations ror Logic Functions SM Reddy Computers, IEEE Transactions on 100 (11), 1183-1188, 1972 | 482 | 1972 |
| COMPACTEST: A method to generate compact test sets for combinational circuits I Pomeranz, LN Reddy, SM Reddy Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1993 | 462 | 1993 |
| Techniques for minimizing power dissipation in scan and combinational circuits during test application V Dabholkar, S Chakravarty, I Pomeranz, S Reddy Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1998 | 379 | 1998 |
| Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits S Kajihara, I Pomeranz, K Kinoshita, SM Reddy Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1995 | 334 | 1995 |
| On Determining Scan Flip-Flops in Partial-Scan Designs. DH Lee, SM Reddy ICCAD, 322-325, 1990 | 303 | 1990 |
| Preferred fill: A scalable method to reduce capture power for scan based designs S Remersaro, X Lin, Z Zhang, SM Reddy, I Pomeranz, J Rajski Test Conference, 2006. ITC'06. IEEE International, 1-10, 2006 | 298 | 2006 |
| Distributed fault-tolerance for large multiprocessor systems JG Kuhl, SM Reddy Proceedings of the 7th annual symposium on Computer Architecture, 23-30, 1980 | 279 | 1980 |
| Authors' Reply< sup> 2</sup> DK Pradhan, SM Reddy IEEE Transactions on Computers 24 (7), 758-759, 1975 | 277* | 1975 |
| A fault-tolerant communication architecture for distributed systems DK Pradhan, SM Reddy IEEE transactions on Computers 31 (9), 863-870, 1982 | 276 | 1982 |
| A march test for functional faults in semiconductor random access memories DS Suk, SM Reddy Computers, IEEE Transactions on 100 (12), 982-985, 1981 | 245 | 1981 |
| On path selection in combinational logic circuits WN Li, SM Reddy, SK Sahni Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1989 | 235 | 1989 |
| On the detection of delay faults AK Pramanick, SM Reddy Test Conference, 1988. Proceedings. New Frontiers in Testing, International …, 1988 | 225 | 1988 |
| Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm Y Huang, SM Reddy, WT Cheng, P Reuter, N Mukherjee, CC Tsai, ... Test Conference, 2002. Proceedings. International, 74-82, 2002 | 213 | 2002 |
| An automatic test pattern generator for the detection of path delay faults SM Reddy, CJ Lin, S Patil proc. ICCAD 87, 284-287, 1987 | 204 | 1987 |
| A diagnosis algorithm for distributed computing systems with dynamic failure and repair SH Hosseini, JG Kuhl, SM Reddy Computers, IEEE Transactions on 100 (3), 223-233, 1984 | 198 | 1984 |
| 3-weight pseudo-random test generation based on a deterministic test set I Pomeranz, SM Reddy VLSI Design, 1992. Proceedings., The Fifth International Conference on, 148-153, 1992 | 196* | 1992 |
| Robust tests for stuck-open faults in CMOS combinational logic circuits SM Reddy, MK Reddy, VD Agrawal Proc. Int. Symp. on Fault-Tolerant Computing, 44-49, 1984 | 188 | 1984 |
| Resource allocation and test scheduling for concurrent test of core-based SOC design Y Huang, WT Cheng, CC Tsai, N Mukherjee, O Samman, Y Zaidan, ... Test Symposium, 2001. Proceedings. 10th Asian, 265-270, 2001 | 186 | 2001 |
| 3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits I Pomeranz, SM Reddy Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1993 | 186 | 1993 |
