Irith Pomeranz
Irith Pomeranz
Email verificata su ecn.purdue.edu
TitoloCitata daAnno
Transient-fault recovery for chip multiprocessors
M Gomaa, C Scarbrough, TN Vijaykumar, I Pomeranz
30th Annual International Symposium on Computer Architecture, 2003 …, 2003
4272003
COMPACTEST: A method to generate compact test sets for combinational circuits
I Pomeranz, LN Reddy, SM Reddy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993
4241993
Transient-fault recovery using simultaneous multithreading
TN Vijaykumar, I Pomeranz, K Cheng
Proceedings 29th Annual International Symposium on Computer Architecture, 87-98, 2002
4032002
Techniques for minimizing power dissipation in scan and combinational circuits during test application
V Dabholkar, S Chakravarty, I Pomeranz, S Reddy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
3501998
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
S Kajihara, I Pomeranz, K Kinoshita, SM Reddy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
3021995
Preferred fill: A scalable method to reduce capture power for scan based designs
S Remersaro, X Lin, Z Zhang, SM Reddy, I Pomeranz, J Rajski
2006 IEEE International Test Conference, 1-10, 2006
2512006
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits
I Pomeranz, SM Reddy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993
1761993
On static compaction of test sequences for synchronous sequential circuits
I Pomeranz, SM Reddy
Proceedings of the 33rd annual Design Automation Conference, 215-220, 1996
1491996
Vector restoration based static compaction of test sequences for synchronous sequential circuits
I Pomeranz, SM Reddy
Proceedings International Conference on Computer Design VLSI in Computers …, 1997
1351997
On the generation of small dictionaries for fault location
I Pomeranz, SM Reddy
ICCAD 92 (1992), 272-279, 1992
1331992
On test data volume reduction for multiple scan chain designs
SM Reddy, K Miyase, S Kajihara, I Pomeranz
ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003
1322003
On n-detection test sets and variable n-detection test sets for transition faults
I Pomeranz, SM Reddy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000
1302000
SOC test scheduling using simulated annealing
W Zou, SM Reddy, I Pomeranz, Y Huang
Proceedings. 21st VLSI Test Symposium, 2003., 325-330, 2003
1292003
Fault dictionary compression and equivalence class computation for sequential circuits
PG Ryan, WK Fuchs, I Pomeranz
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD …, 1993
1121993
NEST: A nonenumerative test generation method for path delay faults in combinational circuits
I Pomeranz, SM Reddy, P Uppaluri
IEEE transactions on computer-aided design of integrated circuits and …, 1995
1041995
Classification of faults in synchronous sequential circuits
I Pomeranz, SM Reddy
IEEE Transactions on Computers 42 (9), 1066-1077, 1993
1031993
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.
H Tang, SM Reddy, I Pomeranz
ITC 3, 1079-1088, 2003
1022003
On the generation of scan-based test sets with reachable states for testing under functional operation conditions
I Pomeranz
Proceedings of the 41st annual Design Automation Conference, 928-933, 2004
1012004
Generation of functional broadside tests for transition faults
I Pomeranz, SM Reddy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1002006
On reducing peak current and power during test
W Li, SM Reddy, I Pomeranz
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design …, 2005
1002005
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