Fatih Hamzaoglu
Fatih Hamzaoglu
Email verificata su intel.com
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A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ...
IEEE Journal of Solid-State Circuits 41 (1), 146-151, 2005
4112005
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ...
IEEE Journal of Solid-State Circuits 40 (4), 895-901, 2005
2642005
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry
E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, U Bhattacharya, K Zhang, ...
2012 IEEE International Solid-State Circuits Conference, 230-232, 2012
1972012
Circuit-level techniques to control gate leakage for sub-100nm CMOS
F Hamzaoglu, MR Stan
Proceedings of the 2002 international symposium on Low power electronics andá…, 2002
1732002
A 1.1 GHz 12 A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
Y Wang, HJ Ahn, U Bhattacharya, Z Chen, T Coan, F Hamzaoglu, ...
IEEE Journal of Solid-State Circuits 43 (1), 172-179, 2008
1262008
Multi-phase 1 GHz voltage doubler charge pump in 32 nm logic process
D Somasekhar, B Srinivasan, G Pandya, F Hamzaoglu, M Khellah, ...
IEEE Journal of Solid-State Circuits 45 (4), 751-758, 2010
1102010
Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation
F Hamzaoglu, Y Te, A Keshavarzi, K Zhang, S Narendra, S Borkar, M Stan, ...
Proceedings of the 2000 international symposium on Low power electronics andá…, 2000
892000
SRAM design on 65nm CMOS technology with integrated leakage reduction scheme
K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ...
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. Noá…, 2004
852004
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management
Y Wang, U Bhattacharya, F Hamzaoglu, P Kolar, Y Ng, L Wei, Y Zhang, ...
2009 IEEE International Solid-State Circuits Conference-Digest of Technicalá…, 2009
752009
MRAM as embedded non-volatile memory solution for 22FFL FinFET technology
O Golonzka, JG Alzate, U Arslan, M Bohr, P Bai, J Brockman, B Buford, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.1. 1-18.1. 4, 2018
682018
A 256-Kb Dual- SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor
M Khellah, D Somasekhar, Y Ye, NS Kim, J Howard, G Ruhl, M Sunna, ...
IEEE Journal of Solid-State Circuits 42 (1), 233-242, 2006
662006
Analysis of dual-V/sub T/SRAM cells with full-swing single-ended bit line sensing for on-chip cache
F Hamzaoglu, Y Ye, A Keshavarzi, K Zhang, S Narendra, S Borkar, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (2), 91-95, 2002
632002
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology
F Hamzaoglu, K Zhang, Y Wang, HJ Ahn, U Bhattacharya, Z Chen, YG Ng, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technicalá…, 2008
622008
A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry
E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, M Meterelliyoz, J Keane, ...
IEEE Journal of Solid-State Circuits 48 (1), 150-158, 2012
582012
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation
H Nho, P Kolar, F Hamzaoglu, Y Wang, E Karl, YG Ng, U Bhattacharya, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 346-347, 2010
562010
A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology
F Hamzaoglu, K Zhang, Y Wang, HJ Ahn, U Bhattacharya, Z Chen, YG Ng, ...
IEEE Journal of Solid-State Circuits 44 (1), 148-154, 2008
562008
A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k+ metal-gate CMOS technology with integrated power management
Y Wang, U Bhattacharya, F Hamzaoglu, P Kolar, YG Ng, L Wei, Y Zhang, ...
IEEE journal of solid-state circuits 45 (1), 103-110, 2009
532009
A 4.2 GHz 0.3 mm2 256kb Dual-V/sub cc/SRAM Building Block in 65nm CMOS
M Khellah, NS Kim, J Howard, G Ruhl, M Sunna, Y Ye, J Tschanz, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technicalá…, 2006
522006
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology
F Hamzaoglu, U Arslan, N Bisnik, S Ghosh, MB Lal, N Lindert, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technicalá…, 2014
512014
13.3 a 7mb stt-mram in 22ffl finfet technology with 4ns read sensing time at 0.9 v using write-verify-write scheme and offset-cancellation sensing technique
L Wei, JG Alzate, U Arslan, J Brockman, N Das, K Fischer, T Ghani, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 214-216, 2019
472019
Il sistema al momento non pu˛ eseguire l'operazione. Riprova pi¨ tardi.
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