Mariam Sadaka
Mariam Sadaka
Senior Fellow @ Soitec
Email verificata su soitec.com
Titolo
Citata da
Citata da
Anno
Inverse slope isolation and dual surface orientation integration
MG Sadaka, D Eades, J Mogab, B Nguyen, MO Zavala, GS Spencer
US Patent 7,575,968, 2009
2082009
Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region
M Sadaka, I Radu
US Patent 8,461,017, 2013
1412013
Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking
I Radu, D Landru, G Gaudin, G Riou, C Tempesta, F Letertre, L Di Cioccio, ...
2010 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2010
1302010
Advanced RF enhancement-mode FETs with improved gate properties
MJ Martinez, E Schirmann, OL Hartin, CG Rampley, MG Sadaka, ...
US Patent 6,893,947, 2005
1272005
Semiconductor device structure and method therefor
TR White, AL Barr, B Nguyen, MK Orlowski, MG Sadaka, V Thean
US Patent 7,226,833, 2007
1232007
Low temperature direct wafer to wafer bonding for 3D integration
G Gaudin, G Riou, M Sadaka, K Winstel, E Kinser
3D Systems Integration Conference (3DIC), IEEE, 16-18, 2010
1192010
Building blocks for wafer-level 3D integration
M Sadaka, L Di Cioccio
Solid State Technology 52 (10), 20-24, 2009
1192009
Direct bonding for wafer level 3D integration
L Di Cioccio, I Radu, P Gueguen, M Sadaka
2010 IEEE International Conference on Integrated Circuit Design and…, 2010
1142010
Semiconductor structure having strained semiconductor and method therefor
AL Barr, D Jovanovic, B Nguyen, MG Sadaka, V Thean, TR White
US Patent 7,205,210, 2007
792007
Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
V Thean, MG Sadaka, TR White, AL Barr, VR Kolagunta, B Nguyen, ...
US Patent 7,018,901, 2006
712006
Method of making a dual strained channel semiconductor device
MG Sadaka, AL Barr, D Jovanovic, B Nguyen, V Thean, SG Thomas, ...
US Patent 7,282,402, 2007
652007
Low RC product transistors in SOI semiconductor process
AL Barr, OO Adetutu, B Nguyen, MK Orlowski, MG Sadaka, V Thean, ...
US Patent 7,037,795, 2006
632006
High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation
B Brar, W Ha, M Sadaka, C Nguyen
US Patent App. 11/711,340, 2007
622007
Dual surface SOI by lateral epitaxial overgrowth
BA Winstead, O Zia, MG Sadaka, MK Orlowski
US Patent 7,435,639, 2008
592008
Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
M Sadaka, I Radu, D Landru
US Patent 8,716,105, 2014
522014
Twisted dual-substrate orientation (DSO) substrates
TR White, L Mathew, B Nguyen, Z Shi, V Thean, MG Sadaka
US Patent 7,803,670, 2010
442010
Double gate device having a heterojunction source/drain and strained channel
V Thean, MG Sadaka, TR White, AL Barr, VR Kolagunta, B Nguyen, ...
US Patent 7,067,868, 2006
442006
Semiconductor device including a lateral field-effect transistor and Schottky diode
MG Sadaka, BPS Brar, W Ha, CNM Nguyen
US Patent 7,655,963, 2010
402010
Modified hybrid orientation technology
OO Adetutu, MG Sadaka, TR White, B Nguyen
US Patent 7,524,707, 2009
382009
Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
V Thean, J Chen, B Nguyen, MG Sadaka, D Zhang
US Patent 7,575,975, 2009
352009
Il sistema al momento non pu eseguire l'operazione. Riprova pi tardi.
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