| Phase change memory HSP Wong, S Raoux, SB Kim, J Liang, JP Reifenberg, B Rajendran, ... Proceedings of the IEEE 98 (12), 2201-2227, 2010 | 1552 | 2010 |
| Phase change memory technology GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ... Journal of Vacuum Science & Technology B, Nanotechnology and …, 2010 | 937 | 2010 |
| A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons J Seo, B Brezzo, Y Liu, BD Parker, SK Esser, RK Montoye, B Rajendran, ... 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 344 | 2011 |
| Write strategies for 2 and 4-bit multi-level phase-change memory T Nirschl, JB Philipp, TD Happ, GW Burr, B Rajendran, MH Lee, A Schrott, ... 2007 IEEE International Electron Devices Meeting, 461-464, 2007 | 305 | 2007 |
| Neuromorphic computing with multi-memristive synapses I Boybat, M Le Gallo, SR Nandakumar, T Moraitis, T Parnell, T Tuma, ... Nature communications 9 (1), 1-12, 2018 | 280 | 2018 |
| Silicon nanowires for sequence-specific DNA sensing: device fabrication and simulation Z Li, B Rajendran, TI Kamins, X Li, Y Chen, RS Williams Applied Physics A 80 (6), 1257-1263, 2005 | 161 | 2005 |
| Nanoscale electronic synapses using phase change devices BL Jackson, B Rajendran, GS Corrado, M Breitwisch, GW Burr, R Cheek, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (2), 1-20, 2013 | 159 | 2013 |
| Specifications of nanoscale devices and circuits for neuromorphic computational systems B Rajendran, Y Liu, J Seo, K Gopalakrishnan, L Chang, DJ Friedman, ... IEEE Transactions on Electron Devices 60 (1), 246-253, 2012 | 155 | 2012 |
| Phase Change Memory: From Devices to Systems MK Qureshi, S Gurumurthi, B Rajendran Synthesis Lectures on Computer Architecture 6 (4), 1-134, 2011 | 148 | 2011 |
| Novel lithography-independent pore phase change memory M Breitwisch, T Nirschl, CF Chen, Y Zhu, MH Lee, M Lamorey, GW Burr, ... 2007 IEEE Symposium on VLSI Technology, 100-101, 2007 | 140 | 2007 |
| Sequential 3D IC fabrication-Challenges and prospects B Rajendran 23rd International VLSI Multilevel Interconnection Conference, VMIC 2006, 2006 | 129 | 2006 |
| Efficient Scrub Mechanisms for Error-Prone Emerging Memories M Awasthi, M Shevgoor, K Sudan, B Rajendran, R Balasubramonian, ... IEEE International Symposium on High Performance Computer Architecture, 2012 | 127 | 2012 |
| Nano-graphoepitaxy of semiconductors for 3D integration F Crnogorac, DJ Witte, Q Xia, B Rajendran, DS Pickard, Z Liu, A Mehta, ... Microelectronic Engineering 84 (5-8), 891-894, 2007 | 123 | 2007 |
| Electrical Integrity of MOS Devices in Laser Annealed 3D IC Structures B Rajendran, RS Shenoy, MO Thompson, RFW Pease proceedings VLSI Multi Level Interconnect Conference, 73-74, 2004 | 115 | 2004 |
| Thermal Simulation of Laser Annealing for 3D Integration B Rajendran, SH Jain, TA Kramer, RFW Pease VMIC, 2003 | 115 | 2003 |
| CMOS transistor processing compatible with monolithic 3-D Integration B Rajendran, RS Shenoy, DJ Witte, NS Chokshi, RL DeLeon, GS Tompa, ... 22nd International VLSI Multilevel Interconnection Conference, VMIC 2005, 2005 | 114 | 2005 |
| Novel synaptic memory device for neuromorphic computing S Mandal, A El-Amin, K Alexander, B Rajendran, R Jha Nature Scientific Reports 4 (5333), 2014 | 89 | 2014 |
| Spiking neural networks for handwritten digit recognition—Supervised learning and network optimization SR Kulkarni, B Rajendran Neural Networks 103, 118-127, 2018 | 81 | 2018 |
| Neuromorphic computing based on emerging memory technologies B Rajendran, F Alibart IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (2 …, 2016 | 68 | 2016 |
| A 250 mV Cu/SiO2/W Memristor with Half-Integer Quantum Conductance States SR Nandakumar, M Minvielle, S Nagar, C Dubourdieu, B Rajendran Nano letters 16 (3), 1602-1608, 2016 | 62 | 2016 |
