Arash Ardakani
Arash Ardakani
Email verificata su mail.mcgill.ca
TitoloCitata daAnno
VLSI implementation of deep neural network using integral stochastic computing
A Ardakani, F Leduc-Primeau, N Onizawa, T Hanyu, WJ Gross
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
842017
Sparsely-connected neural networks: towards efficient VLSI implementation of deep neural networks
A Ardakani, C Condo, WJ Gross
International Conference on Learning Representations (ICLR) 2017, 2017
232017
An architecture to accelerate convolution in deep neural networks
A Ardakani, C Condo, M Ahmadi, WJ Gross
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1349-1362, 2017
202017
Stochastic computing can improve upon digital spiking neural networks
SC Smithson, K Boga, A Ardakani, BH Meyer, WJ Gross
2016 IEEE International Workshop on Signal Processing Systems (SiPS), 309-314, 2016
132016
A novel area-efficient vlsi architecture for recursion computation in lte turbo decoders
A Ardakani, M Shabany
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (6), 568-572, 2015
122015
An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding
A Ardakani, M Mahdavi, M Shabany
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 797-800, 2013
82013
Design and implementation of a polar codes blind detection scheme
C Condo, SA Hashemi, A Ardakani, F Ercan, WJ Gross
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (6), 943-947, 2018
72018
Hardware implementation of FIR/IIR digital filters using integral stochastic computation
A Ardakani, F Leduc-Primeau, WJ Gross
2016 IEEE International Conference on Acoustics, Speech and Signal …, 2016
72016
A convolutional accelerator for neural networks with binary weights
A Ardakani, C Condo, WJ Gross
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
62018
An efficient max-log MAP algorithm for VLSI implementation of turbo decoders
A Ardakani, M Shabany
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1794-1797, 2015
62015
Activation pruning of deep convolutional neural networks
A Ardakani, C Condo, WJ Gross
2017 IEEE Global Conference on Signal and Information Processing (GlobalSIP …, 2017
22017
Learning to Skip Ineffectual Recurrent Computations in LSTMs
A Ardakani, Z Ji, WJ Gross
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, 2019
12019
Multi-Mode Inference Engine for Convolutional Neural Networks
A Ardakani, C Condo, WJ Gross
arXiv preprint arXiv:1712.03994, 2017
12017
Fast and Efficient Convolutional Accelerator for Edge Computing
A Ardakani, C Condo, WJ Gross
IEEE Transactions on Computers, 2019
2019
The Synthesis of XNOR Recurrent Neural Networks with Stochastic Logic
A Ardakani, Z Ji, A Ardakani, W Gross
2019
Learning Recurrent Binary/Ternary Weights
A Ardakani, Z Ji, SC Smithson, BH Meyer, WJ Gross
International Conference on Learning Representations (ICLR) 2019, 2019
2019
A Multi-Mode Accelerator for Pruned Deep Neural Networks
A Ardakani, C Condo, WJ Gross
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS …, 2018
2018
A low-complexity fully scalable interleaver/address generator based on a novel property of QPP interleavers
A Ardakani, M Shabany
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
2017
2015 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 62
M Aamir, E Abbe, T Abraham, MO Ahmad, CK Ahn, H Alasti, G Allan, ...
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS 62 (12), 1205, 2015
2015
SiPS 2016 Additional Reviewers
KE Abdelouahab, M Ahmadi, M Amiri, S Anwar, A Ardakani, H Aurora, ...
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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