Sandro Bartolini
Sandro Bartolini
University of Siena - Department of Information Engineering and Mathematical Sciences
Email verificata su - Home page
Citata da
Citata da
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis
L Ramini, P Grani, S Bartolini, D Bertozzi
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE…, 2013
Design options for optical ring interconnect in future client devices
P Grani, S Bartolini
ACM Journal on Emerging Technologies in Computing Systems (JETC) 10 (4), 1-25, 2014
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline
L Ramini, A Ghiribaldi, P Grani, S Bartolini, HT Fankem, D Bertozzi
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
A performance evaluation of ARM ISA extension for elliptic curve cryptography over binary finite fields
S Bartolini, I Branovic, R Giorgi, E Martinelli
16th Symposium on Computer Architecture and High Performance Computing, 238-245, 2004
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF (2/sup m/)
S Bartolini, I Branovic, R Giorgi, E Martinelli
IEEE Transactions on Computers 57 (5), 672-685, 2008
Instruction cache energy saving through compiler way-placement
TM Jones, S Bartolini, B De Bus, J Cavazos, MFP O'Boyle
Proceedings of the conference on Design, automation and test in Europe, 1196…, 2008
A simple on-chip optical interconnection for improving performance of coherency traffic in cmps
S Bartolini, P Grani
2012 15th Euromicro Conference on Digital System Design, 312-318, 2012
Optimizing instruction cache performance of embedded systems
S Bartolini, CA Prete
ACM Transactions on Embedded Computing Systems (TECS) 4 (4), 934-965, 2005
Feedback-driven restructuring of multi-threaded applications for NUCA cache performance in CMPs
S Bartolini, P Foglia, M Solinas, CA Prete
2010 22nd International Symposium on Computer Architecture and High…, 2010
Instruction set extensions for cryptographic applications
S Bartolini, R Giorgi, E Martinelli
Cryptographic Engineering, 191-233, 2009
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems
S Bartolini, P Foglia, CA Prete
Future Generation Computer Systems 78, 481-501, 2018
Olympic: A hierarchical all-optical photonic network for low-power chip multiprocessors
S Bartolini, L Lusnig, E Martinelli
2013 Euromicro Conference on Digital System Design, 56-59, 2013
Simultaneous optical path-setup for reconfigurable photonic networks in tiled CMPS
P Grani, S Bartolini
2014 IEEE Intl Conf on High Performance Computing and Communications, 2014…, 2014
Augmented virtuality for coastal management: A holistic use of in situ and remote sensing for large scale definition of coastal dynamics
S Bartolini, A Mecocci, A Pozzebon, C Zoppetti, D Bertoni, G Sarti, A Caiti, ...
ISPRS International Journal of Geo-Information 7 (3), 92, 2018
Managing resources dynamically in hybrid photonic‐electronic networks‐on‐chip
A Garca‐Guirado, R Fernndez‐Pascual, JM Garca, S Bartolini
Concurrency and Computation: Practice and Experience 26 (15), 2530-2550, 2014
Sistema per la Traduzione in Lingua Italiana dei Segni: Blue Sign Translator/Wireless Sign System
S Bartolini, P Bennati, R Giorgi
Proc. of the 50th AIES National Conference, 2004
Link-time optimization for power efficiency in a tagless instruction cache
TM Jones, S Bartolini, J Maebe, D Chanet
International Symposium on Code Generation and Optimization (CGO 2011), 32-41, 2011
A software strategy to improve cache performance
S Bartolini, CA Prete
IEEE TCCA Newsletter, 24-32, 2001
Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs
B Peccerillo, S Bartolini, K Ko
Journal of Cryptographic Engineering 9 (2), 159-171, 2019
PHAST-A portable high-level modern C++ programming library for GPUs and multi-cores
B Peccerillo, S Bartolini
IEEE Transactions on Parallel and Distributed Systems 30 (1), 174-189, 2018
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