| Architecture and Design Flow for a Highly Efficient Structured ASIC MH Ho, YQ Ai, TCP Chau, SCL Yuen, CS Choy, PHW Leong, KP Pun | 26 | |
| Towards FPGA-assisted spark: An SVM training acceleration case study SMH Ho, M Wang, HC Ng, HKH So 2016 International Conference on ReConFigurable Computing and FPGAs …, 2016 | 6 | 2016 |
| Structured ASIC: Methodology and comparison SMH Ho, SCL Yuen, HC Poon, TCP Chau, YQ Ai, PHW Leong, OCS Choy, ... 2010 International Conference on Field-Programmable Technology, 377-380, 2010 | 5 | 2010 |
| Design of a single layer programmable structured ASIC library TCP Chau, DWL Wu, YQ Ai, BPW Chan, SMH Ho, OKL Lau, SCL Yuen, ... 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010 | 5 | 2010 |
| A comparison of via-programmable gate array logic cell circuits TCP Chau, PHW Leong, SMH Ho, BPW Chan, SCL Yuen, KP Pun, ... Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2009 | 5 | 2009 |
| Rapid prototyping on a structured ASIC fabric SCL Yuen, YQ Ai, BPW Chan, TCP Chau, SMH Ho, OKL Lau, KP Pun, ... 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 379-380, 2010 | 2 | 2010 |
| Generation Of Synthetic Floating-point Benchmark Circuits TCP Chau, SMH Ho, PHW Leong, P Zipf, M Glesner 2009 IEEE International Symposium on Parallel & Distributed Processing, 1-9, 2009 | 1 | 2009 |
