| INDEP approach for leakage reduction in nanoscale CMOS circuits VK Sharma, M Pattanaik, B Raj International Journal of Electronics 102 (2), 200-215, 2015 | 80 | 2015 |
| ONOFIC approach: low power high speed nanoscale VLSI circuits design VK Sharma, M Pattanaik, B Raj International Journal of Electronics 101 (1), 61-73, 2014 | 80 | 2014 |
| PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits VK Sharma, M Pattanaik, B Raj Microelectronics reliability 54 (1), 90-99, 2014 | 58 | 2014 |
| Optimal design for digital comparator using QCA nanotechnology with energy estimation VK Sharma International Journal of Numerical Modelling: Electronic Networks, Devices …, 2021 | 38 | 2021 |
| Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology U Mushtaq, VK Sharma International journal of numerical modelling: electronic networks, devices …, 2020 | 37 | 2020 |
| VLSI scaling methods and low power CMOS buffer circuit VK Sharma, M Pattanaik Journal of Semiconductors 34 (9), 095001, 2013 | 37 | 2013 |
| Optimal design for 1:2n demultiplexer using QCA nanotechnology with energy dissipation analysis VK Sharma International Journal of Numerical Modelling: Electronic Networks, Devices …, 2021 | 30 | 2021 |
| Intravitreal dexamethasone implant versus triamcinolone acetonide for macular oedema of central retinal vein occlusion: quantifying efficacy and safety SK Mishra, A Gupta, S Patyal, S Kumar, K Raji, A Singh, V Sharma International Journal of Retina and Vitreous 4, 1-8, 2018 | 29 | 2018 |
| High performance process variations aware technique for sub-threshold 8T-SRAM cell VK Sharma, S Patel, M Pattanaik Wireless personal communications 78 (1), 57-68, 2014 | 28 | 2014 |
| Techniques for low leakage nanoscale VLSI circuits: A comparative study VK Sharma, M Pattanaik Journal of Circuits, Systems, and Computers 23 (05), 1450061, 2014 | 27 | 2014 |
| CNTFET circuit-based wide fan-in domino logic for low power applications VK Sharma Journal of Circuits, Systems and Computers 31 (02), 2250036, 2022 | 26 | 2022 |
| A reliable ground bounce noise reduction technique for nanoscale CMOS circuits VK Sharma, M Pattanaik International Journal of Electronics 102 (11), 1852–1866, 2015 | 26 | 2015 |
| Multioperative reversible gate design with implementation of 1‐bit full adder and subtractor along with energy dissipation analysis S Riyaz, SF Naz, VK Sharma International Journal of Circuit Theory and Applications 49 (4), 990-1012, 2021 | 25 | 2021 |
| Design of low leakage variability aware ONOFIC CMOS standard cell library VK Sharma, M Pattanaik Journal of Circuits, Systems and Computers 25 (11), 1650134, 2016 | 25 | 2016 |
| Leakage power reduction in CMOS logic circuits using stack ONOFIC technique C Kumar, AS Mishra, VK Sharma 2018 Second International Conference on Intelligent Computing and Control …, 2018 | 22 | 2018 |
| A Review of QCA Nanotechnology as an Alternate to CMOS SF Naz, S Riyaz, VK Sharma Current Nanoscience 18 (1), 18-30, 2022 | 21 | 2022 |
| Leakage current ONOFIC approach for deep submicron VLSI circuit design VK Sharma, M Pattanaik, B Raj International Journal of Electrical, Computer, Electronics and Communication …, 2013 | 21 | 2013 |
| Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology S Riyaz, VK Sharma Circuit world 49 (1), 28-37, 2023 | 20 | 2023 |
| A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime VK Sharma Australian journal of electrical and electronics Engineering 18 (4), 217-236, 2021 | 18 | 2021 |
| Process, voltage and temperature variations aware low leakage approach for nanoscale CMOS circuits VK Sharma, M Pattanaik Journal of Low Power Electronics 10 (1), 45-52, 2014 | 18 | 2014 |
Dr. Manisha PattanaikProfessor, ABV-IIITM Gwalior (INDIA)Verified email at iiitm.ac.in
