| Coverage driven test generation framework for RTL functional verification Y Guo, W Qu, T Li, S Li 2007 10th IEEE International Conference on Computer-Aided Design and …, 2007 | 26 | 2007 |
| Design and implementation of a parallel verilog simulator: Pvsim T Li, Y Guo, SK Li 17th International Conference on VLSI Design. Proceedings., 329-334, 2004 | 26 | 2004 |
| MA/sup 2/TG: a functional test program generator for microprocessor verification T Li, D Zhu, Y Guo, GJ Liu, SK Li 8th Euromicro Conference on Digital System Design (DSD'05), 176-183, 2005 | 19 | 2005 |
| A unified approach to teach computational thinking for first year non–cs majors in an introductory course T Li, T Wang IERI Procedia 2, 498-503, 2012 | 18 | 2012 |
| The use of UML sequence diagram for system-on-chip system level transaction-based functional verification JS Yu, T Li, QP Tan 2006 6th World Congress on Intelligent Control and Automation 2, 6173-6177, 2006 | 18 | 2006 |
| Translation validation of scheduling in high level synthesis T Li, Y Guo, W Liu, M Tang Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 17 | 2013 |
| Efficient translation validation of high-level synthesis T Li, Y Guo, W Liu, C Ma International Symposium on Quality Electronic Design (ISQED), 516-523, 2013 | 15 | 2013 |
| 谓词抽象技术研究 屈婉霞， 李暾， 郭阳， 杨晓东 软件学报 19 (1), 27-38, 2008 | 15 | 2008 |
| Symbolic simulation enhanced coverage-directed fuzz testing of rtl design T Li, H Zou, D Luo, W Qu 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 13 | 2021 |
| Equivalence checking between SLM and RTL using machine learning techniques J Hu, T Li, S Li 2016 17th International Symposium on Quality Electronic Design (ISQED), 129-134, 2016 | 12 | 2016 |
| Functional vectors generation for RT-level Verilog descriptions based on path enumeration and constraint logic programming T Li, Y Guo, GJ Liu, S Li 8th Euromicro Conference on Digital System Design (DSD'05), 17-23, 2005 | 12 | 2005 |
| Advances in predicate abstraction WX Qu, T Li, Y Guo, XD Yang Journal of Software 19 (1), 27-38, 2008 | 11 | 2008 |
| An automatic circuit extractor for rtl verification T Li, Y Guo, S Li 2003 Test Symposium, 154-160, 2003 | 11 | 2003 |
| Equivalence checking between SLM and TLM using coverage directed simulation J Hu, T Li, S Li Frontiers of Computer Science 9, 934-943, 2015 | 10 | 2015 |
| 2D Decomposition sequential equivalence checking of system level and RTL descriptions D Zhu, T Li, Y Guo, S Li 9th International Symposium on Quality Electronic Design (isqed 2008), 637-642, 2008 | 9 | 2008 |
| Fast panorama unrolling of catadioptric omni-directional images for cooperative robot vision system Z Xiong, M Zhang, Y Wang, T Li, S Li 2007 11th International Conference on Computer Supported Cooperative Work in …, 2007 | 8 | 2007 |
| Feature-oriented refactoring proposal for transaction level models in SoCLib J Ye, Q Tan, T Li, B Wu, Y Meng 2010 Forum on Specification & Design Languages (FDL 2010), 1-6, 2010 | 7 | 2010 |
| Equivalence checking of scheduling in high-level synthesis T Li, J Hu, Y Guo, S Li, Q Tan Sixteenth International Symposium on Quality Electronic Design, 257-262, 2015 | 6 | 2015 |
| The application of aspectual feature module in the development and verification of SystemC models Y Jun, L Tun, T Qingping 2009 Forum on Specification & Design Languages (FDL), 1-6, 2009 | 6 | 2009 |
| Automatic circuit extractor for HDL description using program slicing T Li, Y Guo, SK Li Journal of Computer Science and Technology 19 (5), 718-728, 2004 | 6 | 2004 |
