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Seyedhamidreza Motaman
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Impact of process-variations in STTRAM and adaptive boosting for robustness
S Motaman, S Ghosh, N Rathi
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
572015
A novel slope detection technique for robust STTRAM sensing
S Motaman, S Ghosh, JP Kulkarni
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
292015
Domain wall memory-layout, circuit and synergistic systems
S Motaman, AS Iyengar, S Ghosh
IEEE Transactions on Nanotechnology 14 (2), 282-291, 2015
292015
Synergistic circuit and system design for energy-efficient and robust domain wall caches
S Motaman, A Iyengar, S Ghosh
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
282014
Adaptive write and shift current modulation for process variation tolerance in domain wall caches
S Motaman, S Ghosh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (3), 944-953, 2015
142015
A perspective on test methodologies for supervised machine learning accelerators
S Motaman, S Ghosh, J Park
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (3 …, 2019
122019
Dynamic computing in memory (DCIM) in resistive crossbar arrays
S Motaman, S Ghosh
2018 IEEE 36th International Conference on Computer Design (ICCD), 179-186, 2018
122018
Threshold defined camouflaged gates in 65nm technology for reverse engineering protection
AS Iyengar, D Vontela, I Reddy, S Ghosh, S Motaman, J Jang
Proceedings of the International Symposium on Low Power Electronics and …, 2018
112018
Overview of circuits, systems, and applications of spintronics
S Ghosh, A Iyengar, S Motaman, R Govindaraj, JW Jang, J Chung, J Park, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (3 …, 2016
112016
Cache bypassing and checkpointing to circumvent data security attacks on STTRAM
S Motaman, S Ghosh, N Rathi
IEEE Transactions on Emerging Topics in Computing 7 (2), 262-270, 2017
72017
VFAB: A novel 2-stage STTRAM sensing using voltage feedback and boosting
S Motaman, S Ghosh, JP Kulkarni
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 1919-1928, 2017
62017
Simultaneous sizing, reference voltage and clamp voltage biasing for robustness, self-calibration and testability of STTRAM arrays
S Motaman, S Ghosh
Proceedings of the 51st Annual Design Automation Conference, 1-2, 2014
62014
Novel application of spintronics in computing, sensing, storage and cybersecurity
S Motaman, MNI Khan, S Ghosh
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 125-130, 2018
52018
Addressing resiliency of in-memory floating point computation
SS Ensan, S Ghosh, S Motaman, D Weast
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (9 …, 2022
12022
A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays
S Motaman, S Ghosh, JW Jang, A Iyengar, R Govindaraj, Z Khondker
arXiv preprint arXiv:2306.03972, 2023
2023
Addressing Resiliency of In-Memory Floating Point Computation
S Sayyah Ensan, S Ghosh, S Motaman, D Weast
arXiv e-prints, arXiv: 2011.00648, 2020
2020
Low Power, Secure and Robust Designs of Non-volatile Memories
S Motaman
The Pennsylvania State University, 2018
2018
Robust slope detection technique for STTRAM and MRAM sensing
S Ghosh, S Motaman
US Patent 9,818,466, 2017
2017
Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing
S Motaman, S Ghosh, J Kulkarni
Journal on Emerging Technologies in Computing Systems (JETC) 14 (1), 8, 2017
2017
Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems........... J. Lee and S. Kim 871 Designing Tunable Subthreshold Logic Circuits Using Adaptive …
M Zangeneh, A Joshi, EP Kim, J Choi, NR Shanbhag, RA Rutenbar, ...
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